Received-SPF: pass (google.com: domain of linux-kernel+bounces-205867-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Message-ID: <751abd157213736e376ca43ef1082362a4ca1149.camel@gmail.com>
Subject: Re: [PATCH v2 2/2] iio: frequency: adf4350: add clk provider
From: Nuno =?ISO-8859-1?Q?S=E1?= <noname.nuno@gmail.com>
To: Antoniu Miclaus <antoniu.miclaus@analog.com>, Lars-Peter Clausen
	 <lars@metafoo.de>, Michael Hennerich <Michael.Hennerich@analog.com>, 
 Jonathan Cameron
	 <jic23@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski
	 <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	linux-iio@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org
Date: Fri, 07 Jun 2024 13:08:30 +0200
In-Reply-To: <20240607095806.3299-2-antoniu.miclaus@analog.com>
References: <20240607095806.3299-1-antoniu.miclaus@analog.com>
	 <20240607095806.3299-2-antoniu.miclaus@analog.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
User-Agent: Evolution 3.52.2 
Precedence: bulk
MIME-Version: 1.0

On Fri, 2024-06-07 at 12:57 +0300, Antoniu Miclaus wrote:
> Add clk provider feature for the adf4350.
>=20
> Even though the driver was sent as an IIO driver in most cases the
> device is actually seen as a clock provider.
>=20
> This patch aims to cover actual usecases requested by users in order to
> completely control the output frequencies from userspace.
>=20
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v2:
> =C2=A0- rework commit title
> =C2=A0drivers/iio/frequency/adf4350.c | 129 +++++++++++++++++++++++++++++=
+++
> =C2=A01 file changed, 129 insertions(+)
>=20
> diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4=
350.c
> index 4abf80f75ef5..1eb8bce71fe1 100644
> --- a/drivers/iio/frequency/adf4350.c
> +++ b/drivers/iio/frequency/adf4350.c
> @@ -19,6 +19,7 @@
> =C2=A0#include <linux/gpio/consumer.h>
> =C2=A0#include <asm/div64.h>
> =C2=A0#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> =C2=A0
> =C2=A0#include <linux/iio/iio.h>
> =C2=A0#include <linux/iio/sysfs.h>
> @@ -31,11 +32,21 @@ enum {
> =C2=A0	ADF4350_PWRDOWN,
> =C2=A0};
> =C2=A0
> +struct adf4350_output {
> +	struct clk_hw hw;
> +	struct iio_dev *indio_dev;
> +};
> +
> +#define to_output(_hw) container_of(_hw, struct adf4350_output, hw)
> +
> =C2=A0struct adf4350_state {
> =C2=A0	struct spi_device		*spi;
> =C2=A0	struct gpio_desc		*lock_detect_gpiod;
> =C2=A0	struct adf4350_platform_data	*pdata;
> =C2=A0	struct clk			*clk;
> +	struct clk			*clkout;
> +	const char			*clk_out_name;
> +	struct adf4350_output		output;
> =C2=A0	unsigned long			clkin;
> =C2=A0	unsigned long			chspc; /* Channel Spacing */
> =C2=A0	unsigned long			fpfd; /* Phase Frequency Detector */
> @@ -264,6 +275,10 @@ static ssize_t adf4350_write(struct iio_dev *indio_d=
ev,
> =C2=A0	mutex_lock(&st->lock);
> =C2=A0	switch ((u32)private) {
> =C2=A0	case ADF4350_FREQ:
> +		if (st->clkout) {
> +			ret =3D clk_set_rate(st->clkout, readin);
> +			break;
> +		}
> =C2=A0		ret =3D adf4350_set_freq(st, readin);
> =C2=A0		break;
> =C2=A0	case ADF4350_FREQ_REFIN:
> @@ -381,6 +396,115 @@ static const struct iio_info adf4350_info =3D {
> =C2=A0	.debugfs_reg_access =3D &adf4350_reg_access,
> =C2=A0};
> =C2=A0
> +static void adf4350_clk_del_provider(void *data)
> +{
> +	struct adf4350_state *st =3D data;
> +
> +	of_clk_del_provider(st->spi->dev.of_node);
> +}
> +
> +static unsigned long adf4350_clk_recalc_rate(struct clk_hw *hw,
> +					=C2=A0=C2=A0=C2=A0=C2=A0 unsigned long parent_rate)
> +{
> +	struct iio_dev *indio_dev =3D to_output(hw)->indio_dev;
> +	struct adf4350_state *st =3D iio_priv(indio_dev);
> +	unsigned long long tmp;
> +
> +	tmp =3D (u64)(st->r0_int * st->r1_mod + st->r0_fract) * st->fpfd;
> +	do_div(tmp, st->r1_mod * (1 << st->r4_rf_div_sel));
> +
> +	return tmp;
> +}
> +
> +static int adf4350_clk_set_rate(struct clk_hw *hw,
> +				unsigned long rate,
> +				unsigned long parent_rate)
> +{
> +	struct iio_dev *indio_dev =3D to_output(hw)->indio_dev;
> +	struct adf4350_state *st =3D iio_priv(indio_dev);
> +
> +	if (parent_rate =3D=3D 0 || parent_rate > ADF4350_MAX_FREQ_REFIN)
> +		return -EINVAL;
> +
> +	st->clkin =3D parent_rate;
> +
> +	return adf4350_set_freq(st, rate);
> +}
> +
> +static int adf4350_clk_prepare(struct clk_hw *hw)
> +{
> +	struct iio_dev *indio_dev =3D to_output(hw)->indio_dev;
> +	struct adf4350_state *st =3D iio_priv(indio_dev);
> +
> +	st->regs[ADF4350_REG2] &=3D ~ADF4350_REG2_POWER_DOWN_EN;
> +
> +	return adf4350_sync_config(st);
> +}
> +
> +static void adf4350_clk_unprepare(struct clk_hw *hw)
> +{
> +	struct iio_dev *indio_dev =3D to_output(hw)->indio_dev;
> +	struct adf4350_state *st =3D iio_priv(indio_dev);
> +
> +	st->regs[ADF4350_REG2] |=3D ADF4350_REG2_POWER_DOWN_EN;
> +
> +	adf4350_sync_config(st);
> +}
> +
> +static int adf4350_clk_is_enabled(struct clk_hw *hw)
> +{
> +	struct iio_dev *indio_dev =3D to_output(hw)->indio_dev;
> +	struct adf4350_state *st =3D iio_priv(indio_dev);
> +
> +	return (st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
> +}
> +
> +static const struct clk_ops adf4350_clk_ops =3D {
> +	.recalc_rate =3D adf4350_clk_recalc_rate,
> +	.set_rate =3D adf4350_clk_set_rate,
> +	.prepare =3D adf4350_clk_prepare,
> +	.unprepare =3D adf4350_clk_unprepare,
> +	.is_enabled =3D adf4350_clk_is_enabled,
> +};
> +
> +static int adf4350_clk_register(struct adf4350_state *st)
> +{
> +	struct spi_device *spi =3D st->spi;
> +	struct clk_init_data init;
> +	struct clk *clk;
> +	const char *parent_name;
> +	int ret;
> +
> +	if (!device_property_present(&spi->dev, "#clock-cells"))
> +		return 0;
> +
> +	init.name =3D devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk",
> +				=C2=A0=C2=A0 fwnode_get_name(dev_fwnode(&spi->dev)));
> +	device_property_read_string(&spi->dev, "clock-output-names",
> +				=C2=A0=C2=A0=C2=A0 &init.name);
> +
> +	parent_name =3D of_clk_get_parent_name(spi->dev.of_node, 0);
> +	if (!parent_name)
> +		return -EINVAL;
> +
> +	init.ops =3D &adf4350_clk_ops;
> +	init.parent_names =3D &parent_name;
> +	init.num_parents =3D 1;
> +
> +	st->output.hw.init =3D &init;
> +	clk =3D devm_clk_register(&spi->dev, &st->output.hw);
> +	if (IS_ERR(clk))
> +		return PTR_ERR(clk);
> +
> +	ret =3D of_clk_add_provider(spi->dev.of_node, of_clk_src_simple_get,
> clk);
> +	if (ret)
> +		return ret;
> +

I totally agree this chip should be a clock provider (maybe it should even =
in
drivers/clk from the beginning) but there's one thing that comes to my mind=
.
Should we still expose the IIO userspace interface in case we register it a=
s a
clock provider?

Sure, we do have clk notifiers in the kernel but I still think it's a sensi=
ble
question :)

I suspect we have another "outliers" in drivers/iio/frequency :)

- Nuno S=C3=A1=20