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Date: Fri, 7 Jun 2024 15:04:06 +0300
From: Vladimir Oltean <olteanv@gmail.com>
To: Martin Schiller <ms@dev.tdt.de>
Cc: martin.blumenstingl@googlemail.com, hauke@hauke-m.de, andrew@lunn.ch,
	f.fainelli@gmail.com, davem@davemloft.net, edumazet@google.com,
	kuba@kernel.org, pabeni@redhat.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 02/13] net: dsa: lantiq_gswip: Only allow
 phy-mode = "internal" on the CPU port
Message-ID: <20240607120406.dksbevig2k6vj6uu@skbuf>
References: <20240606085234.565551-1-ms@dev.tdt.de>
 <20240606085234.565551-3-ms@dev.tdt.de>
 <20240607110318.jujco3liryl7om3v@skbuf>
 <bc660eb043143926ef267d1b96dee939@dev.tdt.de>
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In-Reply-To: <bc660eb043143926ef267d1b96dee939@dev.tdt.de>

On Fri, Jun 07, 2024 at 02:01:57PM +0200, Martin Schiller wrote:
> On 2024-06-07 13:03, Vladimir Oltean wrote:
> > On Thu, Jun 06, 2024 at 10:52:23AM +0200, Martin Schiller wrote:
> > > From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > > 
> > > Add the CPU port to gswip_xrx200_phylink_get_caps() and
> > > gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal
> > > bus,
> > > so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
> > > 
> > > Signed-off-by: Martin Blumenstingl
> > > <martin.blumenstingl@googlemail.com>
> > > ---
> > 
> > This is for the case where those CPU port device tree properties are
> > present, right? In the device trees in current circulation they are not,
> > and DSA skips phylink registration.
> 
> Yes, as far as I know, this driver is mainly, if not exclusively, used in
> the
> openWrt environment. These functions were already added here in Oct. 2022
> [1].
> 
> [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=2683cca5927844594f7835aa983e2690d1e343c6

Ok. You can add my

Reviewed-by: Vladimir Oltean <olteanv@gmail.com>