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From: Heiko Stuebner <heiko@sntech.de>
To: Linus Walleij <linus.walleij@linaro.org>, Huang-Huang Bao <i@eh5.me>
Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
 Huang-Huang Bao <i@eh5.me>
Subject:
 Re: [PATCH v2 1/4] pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins
Date: Fri, 07 Jun 2024 14:23:52 +0200
Message-ID: <8510397.lOV4Wx5bFT@phil>
In-Reply-To: <20240606125755.53778-2-i@eh5.me>
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 <20240606125755.53778-1-i@eh5.me> <20240606125755.53778-2-i@eh5.me>
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Am Donnerstag, 6. Juni 2024, 14:57:52 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
> recalculated so it remain unchanged.
> 
> The pinmux bits for those pins are not explicitly specified in RK3328
> TRM, however we can get hint from pad name and its correspinding IOMUX
> setting for pins in interface descriptions. The correspinding IOMIX
> settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to
> occurrences of following pad names in RK3328 TRM.
> 
> GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5
> GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5
> GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5
> GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5
> GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5
> GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5
> GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5
> 
> This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
> between GPIO2-B7 with GPIO2-B5.
> 
> Signed-off-by: Huang-Huang Bao <i@eh5.me>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")

The TRM also supports those findings, as gpio2-b4 actually is documented
there as 2-bit wide with the functions you found in the pad descriptions.