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In-Reply-To: <20240606012936.jdokepv73qrdorbp@synopsys.com>
From: joswang <joswang1221@gmail.com>
Date: Fri, 7 Jun 2024 22:07:26 +0800
Message-ID: <CAMtoTm3tSNKdv+LOCeQFtFpGq=6yNqTm8Jq=koFfAxT4UamOQg@mail.gmail.com>
Subject: Re: [PATCH v2, 3/3] usb: dwc3: core: Workaround for CSR read timeout
To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Cc: "robh@kernel.org" <robh@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, 
	"conor+dt@kernel.org" <conor+dt@kernel.org>, 
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>, 
	"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>, 
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "balbi@kernel.org" <balbi@kernel.org>, 
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, joswang <joswang@lenovo.com>
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On Thu, Jun 6, 2024 at 9:29=E2=80=AFAM Thinh Nguyen <Thinh.Nguyen@synopsys.=
com> wrote:
>
> On Tue, Jun 04, 2024, joswang wrote:
> > On Tue, Jun 4, 2024 at 8:07=E2=80=AFAM Thinh Nguyen <Thinh.Nguyen@synop=
sys.com> wrote:
> > >
> > > On Mon, Jun 03, 2024, joswang wrote:
> > > > From: joswang <joswang@lenovo.com>
> > > >
> > > > DWC31 version 2.00a have an issue that would cause
> > > > a CSR read timeout When CSR read coincides with RAM
> > > > Clock Gating Entry.
> > >
> > > Do you have the STAR issue number?
> > >
> > Thanks for reviewing the code.
> > The STAR number provided by Synopsys is 4846132.
> > Please help review further.
>
> I've confirmed internally. As you have noted, this applies to DWC_usb31
> v2.00a for host mode only and DRD mode operating as host.
>
> >
> > > >
> > > > This workaround solution disable Clock Gating, sacrificing
> > > > power consumption for normal operation.
> > > >
> > > > Signed-off-by: joswang <joswang@lenovo.com>
> > > > ---
> > > >  drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++
> > > >  1 file changed, 23 insertions(+)
> > > >
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index 3a8fbc2d6b99..1df85c505c9e 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -978,11 +978,22 @@ static void dwc3_core_setup_global_control(st=
ruct dwc3 *dwc)
> > > >                *
> > > >                * STAR#9000588375: Clock Gating, SOF Issues when ref=
_clk-Based
> > > >                * SOF/ITP Mode Used
>
> Since there's another STAR, let's split the if-else case separately and
> provide the comments separately.
>
OK
> > > > +              *
> > > > +              * WORKAROUND: DWC31 version 2.00a have an issue that=
 would
>
> Can we use the full name DWC_usb31 instead of DWC31.
>
Subsequent V3 versions use DWC_usb31
> > > > +              * cause a CSR read timeout When CSR read coincides w=
ith RAM
> > > > +              * Clock Gating Entry.
> > > > +              *
> > > > +              * This workaround solution disable Clock Gating, sac=
rificing
> > > > +              * power consumption for normal operation.
> > > >                */
> > > >               if ((dwc->dr_mode =3D=3D USB_DR_MODE_HOST ||
> > > >                               dwc->dr_mode =3D=3D USB_DR_MODE_OTG) =
&&
> > > >                               DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
> > > >                       reg |=3D DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SO=
FITPSYNC;
> > > > +             else if ((dwc->dr_mode =3D=3D USB_DR_MODE_HOST ||
> > > > +                             dwc->dr_mode =3D=3D USB_DR_MODE_OTG) =
&&
>
> There's no OTG mode for DWC_usb31. Let's enable this workaround if the
> HW mode is not DWC_GHWPARAMS0_MODE_GADGET.
>
> > > > +                             DWC3_VER_IS(DWC31, 200A))
> > > > +                     reg |=3D DWC3_GCTL_DSBLCLKGTNG;
> > > >               else
> > > >                       reg &=3D ~DWC3_GCTL_DSBLCLKGTNG;
> > > >               break;
> > > > @@ -992,6 +1003,18 @@ static void dwc3_core_setup_global_control(st=
ruct dwc3 *dwc)
> > > >                * will work. Device-mode hibernation is not yet impl=
emented.
> > > >                */
> > > >               reg |=3D DWC3_GCTL_GBLHIBERNATIONEN;
> > > > +
> > > > +             /*
> > > > +              * WORKAROUND: DWC31 version 2.00a have an issue that=
 would
> > > > +              * cause a CSR read timeout When CSR read coincides w=
ith RAM
> > > > +              * Clock Gating Entry.
> > > > +              *
> > > > +              * This workaround solution disable Clock Gating, sac=
rificing
> > > > +              * power consumption for normal operation.
> > > > +              */
> > > > +             if ((dwc->dr_mode =3D=3D USB_DR_MODE_HOST ||
> > > > +                  dwc->dr_mode =3D=3D USB_DR_MODE_OTG) && DWC3_VER=
_IS(DWC31, 200A))
> > > > +                     reg |=3D DWC3_GCTL_DSBLCLKGTNG;
> > > >               break;
> > > >       default:
> > > >               /* nothing */
> > > > --
> > > > 2.17.1
> > > >
> > >
>
> We have the same checks and comments here. Can we refactor?
> Perhaps something this?
>
> power_opt =3D DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
> switch (power_opt) {
>     ...
> }
>
> /*
>  * <comment>
>  */
> if (power_opt !=3D DWC3_GHWPARAMS1_EN_PWROPT_NO) {
> }
>
>
> Thanks,
> Thinh

Thank you for your valuable suggestions.I can refactor according to
your suggestion.
Do I need to submit a V3 version patch separately, or should I submit
a V3 version patch together with other cases?

Thanks,
Jos Wang