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Fri, 7 Jun 2024 15:01:02 GMT Received: from [10.226.59.182] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 7 Jun 2024 08:01:01 -0700 Message-ID: <4370ae55-9521-d2da-62b9-42d26b6fbece@quicinc.com> Date: Fri, 7 Jun 2024 09:01:00 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH v1 1/2] bus: mhi: host: Import link_id item Content-Language: en-US To: Slark Xiao , , , CC: , , References: <20240607100114.452979-1-slark_xiao@163.com> From: Jeffrey Hugo In-Reply-To: <20240607100114.452979-1-slark_xiao@163.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hvNZKNirWtan41QF6CeLjdWGwNd0doC2 X-Proofpoint-ORIG-GUID: hvNZKNirWtan41QF6CeLjdWGwNd0doC2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-07_08,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 clxscore=1011 bulkscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406070110 $Subject says this is patch 1 of 2, but I don't see a second patch nor a cover letter. On 6/7/2024 4:01 AM, Slark Xiao wrote: > For SDX72 MBIM mode, it starts data mux id from 112 instead of 0. > This would lead to device can't ping outside successfully. > Also MBIM side would report "bad packet session (112)". > So we add a link id default value for SDX72. > > Signed-off-by: Slark Xiao > --- > drivers/bus/mhi/host/pci_generic.c | 3 +++ > include/linux/mhi.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index 0b483c7c76a1..1f9de2730766 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -53,6 +53,7 @@ struct mhi_pci_dev_info { > unsigned int dma_data_width; > unsigned int mru_default; > bool sideband_wake; > + unsigned int link_default; > }; > > #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ > @@ -469,6 +470,7 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx72_info = { > .dma_data_width = 32, > .mru_default = 32768, > .sideband_wake = false, > + .link_default = 112, > }; > > static const struct mhi_channel_config mhi_mv3x_channels[] = { > @@ -1035,6 +1037,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > mhi_cntrl->runtime_get = mhi_pci_runtime_get; > mhi_cntrl->runtime_put = mhi_pci_runtime_put; > mhi_cntrl->mru = info->mru_default; > + mhi_cntrl->link_id = info->link_default; > > if (info->edl_trigger) > mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; > diff --git a/include/linux/mhi.h b/include/linux/mhi.h > index b573f15762f8..4da10b99c96e 100644 > --- a/include/linux/mhi.h > +++ b/include/linux/mhi.h > @@ -445,6 +445,7 @@ struct mhi_controller { > bool wake_set; > unsigned long irq_flags; > u32 mru; > + u32 link_id; > }; > > /** None of this is actually used. Dead code is generally not accepted. -Jeff