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Date: Fri, 7 Jun 2024 15:01:43 -0700
From: Deepak Gupta <debug@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] riscv: Per-thread envcfg CSR support
Message-ID: <ZmODR+EMn5zW2Iu1@debug.ba.rivosinc.com>
References: <20240605205658.184399-1-samuel.holland@sifive.com>
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In-Reply-To: <20240605205658.184399-1-samuel.holland@sifive.com>

Hi Samuel,

Thanks for working on these.
Patches looks good to me. I've given some suggestion for patch organization
and squashing. You can take it or leave it.

Other than that.

Reviewed-By: Deepak Gupta <debug@rivosinc.com>

On Wed, Jun 05, 2024 at 01:56:44PM -0700, Samuel Holland wrote:
>This series (or equivalent) is a prerequisite for both user-mode pointer
>masking and CFI support, as those are per-thread features are controlled
>by fields in the envcfg CSR. These patches are based on v1 of the
>pointer masking series[1], with significant input from both Deepak and
>Andrew. By sending this as a separate series, hopefully we can converge
>on a single implementation of this functionality.
>
>[1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/
>
>
>Samuel Holland (3):
>  riscv: Enable cbo.zero only when all harts support Zicboz
>  riscv: Add support for per-thread envcfg CSR values
>  riscv: Call riscv_user_isa_enable() only on the boot hart
>
> arch/riscv/include/asm/cpufeature.h |  2 +-
> arch/riscv/include/asm/processor.h  |  1 +
> arch/riscv/include/asm/switch_to.h  |  8 ++++++++
> arch/riscv/kernel/cpufeature.c      | 13 +++++++++----
> arch/riscv/kernel/smpboot.c         |  2 --
> arch/riscv/kernel/suspend.c         |  4 ++--
> 6 files changed, 21 insertions(+), 9 deletions(-)
>
>-- 
>2.44.1
>