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Mon, 10 Jun 2024 03:56:37 -0500 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45A8uXxw051246; Mon, 10 Jun 2024 03:56:34 -0500 Message-ID: Date: Mon, 10 Jun 2024 14:26:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: ti: am642-phyboard-electra: Add overlay to enable PCIe To: Nathan Morrisson , , , , , CC: , , , , References: <20240513225646.3603803-1-nmorrisson@phytec.com> <20240513225646.3603803-3-nmorrisson@phytec.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <20240513225646.3603803-3-nmorrisson@phytec.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi On 14/05/24 04:26, Nathan Morrisson wrote: > Add an overlay to enable PCIe on the am642-phyboard-electra. This > will disable USB3 and restrict us to USB2. > Commit message still doesn't answer why? Could you explain why the overlay is needed I am guessing USB3 and PCIe are exclusive at SoC level and board has capabilities for both? So, please add the same to commit message. [...] -- Regards Vignesh