Received-SPF: pass (google.com: domain of linux-kernel+bounces-207961-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Date: Mon, 10 Jun 2024 10:44:54 +0100
From: Conor Dooley <conor.dooley@microchip.com>
To: Daire McNamara <daire.mcnamara@microchip.com>
CC: <linux-pci@vger.kernel.org>, Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>, Rob Herring
	<robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 2/2] PCI: microchip: Fix inbound address translation
 tables
Message-ID: <20240610-pointless-hamstring-908149945428@wendy>
References: <20240531085333.2501399-1-daire.mcnamara@microchip.com>
 <20240531085333.2501399-3-daire.mcnamara@microchip.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
	protocol="application/pgp-signature"; boundary="EA8Ls/LOE2pcxK1c"
Content-Disposition: inline
In-Reply-To: <20240531085333.2501399-3-daire.mcnamara@microchip.com>

--EA8Ls/LOE2pcxK1c
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Fri, May 31, 2024 at 09:53:33AM +0100, Daire McNamara wrote:
> On Microchip PolarFire SoC the PCIe Root Port can be behind one of three
> general purpose Fabric Interface Controller (FIC) buses that encapsulates
> an AXI-S bus. Depending on which FIC(s) the Root Port is connected
> through to CPU space, and what address translation is done by that FIC,
> the Root Port driver's inbound address translation may vary.
>=20
> For all current supported designs and all future expected designs,
> inbound address translation done by a FIC on PolarFire SoC varies
> depending on whether PolarFire SoC in operating in dma-coherent mode or
> dma-noncoherent mode.
>=20
> The setup of the outbound address translation tables in the root port
> driver only needs to handle these two cases.
>=20
> Setup the inbound address translation tables to one of two address
> translations, depending on whether the rootport is marked as dma-coherent=
 or
> dma-noncoherent.

Since we're talking about dma-noncoherent here, I think this series
should contain a patch that adds the property to the binding for PCIe:

-- >8 --

=46rom af066543b8f8b8b0b37e0844979f0c3e28f30513 Mon Sep 17 00:00:00 2001
=46rom: Conor Dooley <conor.dooley@microchip.com>
Date: Mon, 20 Mar 2023 11:02:11 +0000
Subject: [PATCH] dt-bindings: PCI: microchip,pcie-host: allow dma-noncohere=
nt

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml=
 b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 45c14b6e4aa4..2f21109c3580 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -53,6 +53,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
=20
+  dma-noncoherent: true
+
   interrupts:
     minItems: 1
     items:
--=20
2.43.2


--EA8Ls/LOE2pcxK1c
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZmbLFgAKCRB4tDGHoIJi
0q9RAQCyVWqWGhytWP+kBJ3WzC7JxIAbVulwqmeberwf5qSR8wD+LHH4hf+EDbaf
t9ZYSsB+xhb1P9hBtrQZ60reOFyN5Ac=
=cgf5
-----END PGP SIGNATURE-----

--EA8Ls/LOE2pcxK1c--