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Petersen" , "daniel@iogearbox.net" , "Williams, Dan J" , "jack@suse.com" , Leon Romanovsky , Zhu Yanjun , "Bommu, Krishnaiah" , "Ghimiray, Himal Prasad" Subject: RE: [RFC RESEND 00/16] Split IOMMU DMA mapping operation to two steps Thread-Topic: [RFC RESEND 00/16] Split IOMMU DMA mapping operation to two steps Thread-Index: AQHanOEtbi0VHTnLn0mNwgftYB7xRbGEmFqggAEftYCAO5ykoA== Date: Mon, 10 Jun 2024 15:12:25 +0000 Message-ID: References: <20240503164239.GB901876@ziepe.ca> In-Reply-To: <20240503164239.GB901876@ziepe.ca> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH7PR11MB7004:EE_|CO1PR11MB5026:EE_ x-ms-office365-filtering-correlation-id: 415cb717-016e-45cd-c3dc-08dc895fbc81 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230031|1800799015|366007|376005|7416005|38070700009; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR11MB7004.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 415cb717-016e-45cd-c3dc-08dc895fbc81 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jun 2024 15:12:25.7198 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dPoMx2tlf098Vc0YA+SzVf+jQQYG+ICixPVfQt+fWbALhBsVt2YFGBnt5FAtkcZdJANKtMcyNPwdRM3Y6QrJDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB5026 X-OriginatorOrg: intel.com Hi Jason, Leon, I come back to this thread to ask a question. Per the discussion in another= thread, I have integrated the new dma-mapping API (the first 6 patches of = this series) to DRM subsystem. The new API seems fit pretty good to our pur= pose, better than scatter-gather dma-mapping. So we want to continue work w= ith you to adopt this new API. Did you test the new API in RDMA subsystem? Or this RFC series was just som= e untested codes sending out to get people's design feedback? Do you have r= efined version for us to try? I ask because we are seeing some issues but n= ot sure whether it is caused by the new API. We are debugging but it would = be good to also ask at the same time. Cc Himal/Krishna who are also working/testing the new API. Thanks, Oak > -----Original Message----- > From: Jason Gunthorpe > Sent: Friday, May 3, 2024 12:43 PM > To: Zeng, Oak > Cc: leon@kernel.org; Christoph Hellwig ; Robin Murphy > ; Marek Szyprowski > ; Joerg Roedel ; Will > Deacon ; Chaitanya Kulkarni ; > Brost, Matthew ; Hellstrom, Thomas > ; Jonathan Corbet ; Jens > Axboe ; Keith Busch ; Sagi > Grimberg ; Yishai Hadas ; > Shameer Kolothum ; Tian, Kevin > ; Alex Williamson ; > J=E9r=F4me Glisse ; Andrew Morton foundation.org>; linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-block@vger.kernel.org; linux-rdma@vger.kernel.org; > iommu@lists.linux.dev; linux-nvme@lists.infradead.org; > kvm@vger.kernel.org; linux-mm@kvack.org; Bart Van Assche > ; Damien Le Moal > ; Amir Goldstein > ; josef@toxicpanda.com; Martin K. Petersen > ; daniel@iogearbox.net; Williams, Dan J > ; jack@suse.com; Leon Romanovsky > ; Zhu Yanjun > Subject: Re: [RFC RESEND 00/16] Split IOMMU DMA mapping operation to > two steps >=20 > On Thu, May 02, 2024 at 11:32:55PM +0000, Zeng, Oak wrote: >=20 > > > Instead of teaching DMA to know these specific datatypes, let's separ= ate > > > existing DMA mapping routine to two steps and give an option to > advanced > > > callers (subsystems) perform all calculations internally in advance a= nd > > > map pages later when it is needed. > > > > I looked into how this scheme can be applied to DRM subsystem and GPU > drivers. > > > > I figured RDMA can apply this scheme because RDMA can calculate the > > iova size. Per my limited knowledge of rdma, user can register a > > memory region (the reg_user_mr vfunc) and memory region's sized is > > used to pre-allocate iova space. And in the RDMA use case, it seems > > the user registered region can be very big, e.g., 512MiB or even GiB >=20 > In RDMA the iova would be linked to the SVA granual we discussed > previously. >=20 > > In GPU driver, we have a few use cases where we need dma-mapping. Just > name two: > > > > 1) userptr: it is user malloc'ed/mmap'ed memory and registers to gpu > > (in Intel's driver it is through a vm_bind api, similar to mmap). A > > userptr can be of any random size, depending on user malloc > > size. Today we use dma-map-sg for this use case. The down side of > > our approach is, during userptr invalidation, even if user only > > munmap partially of an userptr, we invalidate the whole userptr from > > gpu page table, because there is no way for us to partially > > dma-unmap the whole sg list. I think we can try your new API in this > > case. The main benefit of the new approach is the partial munmap > > case. >=20 > Yes, this is one of the main things it will improve. >=20 > > We will have to pre-allocate iova for each userptr, and we have many > > userptrs of random size... So we might be not as efficient as RDMA > > case where I assume user register a few big memory regions. >=20 > You are already doing this. dma_map_sg() does exactly the same IOVA > allocation under the covers. >=20 > > 2) system allocator: it is malloc'ed/mmap'ed memory be used for GPU > > program directly, without any other extra driver API call. We call > > this use case system allocator. >=20 > > For system allocator, driver have no knowledge of which virtual > > address range is valid in advance. So when GPU access a > > malloc'ed/mmap'ed address, we have a page fault. We then look up a > > CPU vma which contains the fault address. I guess we can use the CPU > > vma size to allocate the iova space of the same size? >=20 > No. You'd follow what we discussed in the other thread. >=20 > If you do a full SVA then you'd split your MM space into granuals and > when a fault hits a granual you'd allocate the IOVA for the whole > granual. RDMA ODP is using a 512M granual currently. >=20 > If you are doing sub ranges then you'd probably allocate the IOVA for > the well defined sub range (assuming the typical use case isn't huge) >=20 > > But there will be a true difficulty to apply your scheme to this use > > case. It is related to the STICKY flag. As I understand it, the > > sticky flag is designed for driver to mark "this page/pfn has been > > populated, no need to re-populate again", roughly...Unlike userptr > > and RDMA use cases where the backing store of a buffer is always in > > system memory, in the system allocator use case, the backing store > > can be changing b/t system memory and GPU's device private > > memory. Even worse, we have to assume the data migration b/t system > > and GPU is dynamic. When data is migrated to GPU, we don't need > > dma-map. And when migration happens to a pfn with STICKY flag, we > > still need to repopulate this pfn. So you can see, it is not easy to > > apply this scheme to this use case. At least I can't see an obvious > > way. >=20 > You are already doing this today, you are keeping the sg list around > until you unmap it. >=20 > Instead of keeping the sg list you'd keep a much smaller datastructure > per-granual. The sticky bit is simply a convient way for ODP to manage > the smaller data structure, you don't have to use it. >=20 > But you do need to keep track of what pages in the granual have been > DMA mapped - sg list was doing this before. This could be a simple > bitmap array matching the granual size. >=20 > Looking (far) forward we may be able to have a "replace" API that > allows installing a new page unconditionally regardless of what is > already there. >=20 > Jason