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Date: Mon, 10 Jun 2024 17:03:41 +0100
From: Mark Brown <broonie@kernel.org>
To: Witold Sadowski <wsadowski@marvell.com>
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, robh@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	pthombar@cadence.com
Subject: Re: [PATCH v8 2/4] spi: cadence: Add Marvell xSPI IP overlay changes
Message-ID: <Zmcj3fZ4DF8r_qf0@finisterre.sirena.org.uk>
References: <20240607151831.3858304-1-wsadowski@marvell.com>
 <20240607151831.3858304-3-wsadowski@marvell.com>
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In-Reply-To: <20240607151831.3858304-3-wsadowski@marvell.com>


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On Fri, Jun 07, 2024 at 08:18:29AM -0700, Witold Sadowski wrote:
> This commit adds support for the basic v2 Marvell overlay block. Key
> features included are:
>     - Clock configuration
>     - PHY configuration
>     - Interrupt configuration (enabling)

This feels like it could usefully be split up so these three bits are
separate, and there appear to be other changes buried in here as well.
I can't tell what changes either the PHY or interrupt configuration
might be referencing.

> @@ -295,6 +450,10 @@ static void cdns_xspi_set_interrupts(struct cdns_xsp=
i_dev *cdns_xspi,
>  				     bool enabled)
>  {
>  	u32 intr_enable;
> +	u32 irq_status;
> +
> +	irq_status =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> +	writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> =20
>  	intr_enable =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
>  	if (enabled)

This seems like a separate change which applies to everything, not just
Marvell versions of the IP, and should be split out and explained.

> @@ -319,6 +478,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi=
_dev *cdns_xspi)
>  		return -EIO;
>  	}
> =20
> +	writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
> +	       cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
> +

This wasn't clearly mentioned in the changelog and is again being done
unconditionally for all instances of the IP, probably best to split out
and explain.

> +static void mrvl_ioreadq(void __iomem  *addr, void *buf, int len)
> +{
> +	int i =3D 0;
> +	int rcount =3D len / 8;
> +	int rcount_nf =3D len % 8;
> +	uint64_t tmp;
> +	uint64_t *buf64 =3D (uint64_t *)buf;

Any need to cast away from void * indicates a problem.

> @@ -337,13 +563,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_=
dev *cdns_xspi)
> =20
>  	switch (sdma_dir) {
>  	case CDNS_XSPI_SDMA_DIR_READ:
> -		ioread8_rep(cdns_xspi->sdmabase,
> -			    cdns_xspi->in_buffer, sdma_size);
> +		cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
>  		break;

It's feeling like it might make sense to have an ops structure rather
than sprinkling checks for the Marvell overlay everywhere.

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