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Date: Mon, 10 Jun 2024 23:24:12 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Devi Priya <quic_devipriy@quicinc.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>, bhelgaas@google.com,
	lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org,
	konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH V5 6/6] PCI: qcom: Add support for IPQ9574
Message-ID: <20240610175412.GB7660@thinkpad>
References: <20240512082858.1806694-1-quic_devipriy@quicinc.com>
 <20240512082858.1806694-7-quic_devipriy@quicinc.com>
 <20240530144730.GG2770@thinkpad>
 <f42559f5-9d4c-4667-bf0e-7abfd9983c36@quicinc.com>
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In-Reply-To: <f42559f5-9d4c-4667-bf0e-7abfd9983c36@quicinc.com>

On Mon, Jun 10, 2024 at 11:15:55AM +0530, Devi Priya wrote:
> 
> 
> On 5/30/2024 8:17 PM, Manivannan Sadhasivam wrote:
> > On Sun, May 12, 2024 at 01:58:58PM +0530, devi priya wrote:
> > > The IPQ9574 platform has 4 Gen3 PCIe controllers:
> > > two single-lane and two dual-lane based on SNPS core 5.70a
> > > 
> > > The Qcom IP rev is 1.27.0 and Synopsys IP rev is 5.80a
> > > Added a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0'
> > > which reuses all the members of 'ops_2_9_0' except for the post_init
> > > as the SLV_ADDR_SPACE_SIZE configuration differs between 2_9_0
> > > and 1_27_0.
> > > 
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> > > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> > > Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> > > ---
> > >   Changes in V5:
> > > 	- Rebased on top of the below series which adds support for fetching
> > > 	  clocks from the device tree
> > > 	  https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org/
> > > 
> > >   drivers/pci/controller/dwc/pcie-qcom.c | 36 +++++++++++++++++++++++---
> > >   1 file changed, 32 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 3d2eeff9a876..af36a29c092e 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -106,6 +106,7 @@
> > >   /* PARF_SLV_ADDR_SPACE_SIZE register value */
> > >   #define SLV_ADDR_SPACE_SZ			0x10000000
> > > +#define SLV_ADDR_SPACE_SZ_1_27_0		0x08000000
> > 
> > Can you please explain what this value corresponds to? Even though there is an
> > old value, I didn't get much info earlier on what it is.
> 
> The PARF_SLV_ADDR_SPACE_SIZE register indicates the range of RC accesses
> to the EP's memory space. Default PoR value is 16MB, which seems to be
> sufficient for IPQ9574 SoC.
> As per the memory map, the memory space corresponding to each PCIe region is
> 128Mb. As the older value corresponds to 256Mb we see PCIe enumeration
> failures.

What kind of failure? Is it because kernel is trying to allocate memory region >
128MB range?

> This register should either be updated to 128Mb(0x8000000) or left at the
> PoR value 16Mb (0x1000000).
> 

Ok, so this is essentially the same as the PCI MEM region defined in DT? In that
case, this value should be extracted from DT instead of being hardcoded.

But PCI MEM region range in DT is low on many platforms. Maybe that's due to all
PCIe instances sharing the 256MB range?

- Mani

-- 
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