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Date: Mon, 10 Jun 2024 20:28:22 +0100
From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
	Andy Chiu <andy.chiu@sifive.com>, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 02/13] dt-bindings: thead: add a vlen register length
 property
Message-ID: <20240610-envision-impart-7211e512f987@spud>
References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com>
 <20240609-xtheadvector-v1-2-3fe591d7f109@rivosinc.com>
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On Mon, Jun 10, 2024 at 09:38:06AM -0700, Charlie Jenkins wrote:
> On Mon, Jun 10, 2024 at 05:29:23PM +0100, Conor Dooley wrote:
> > On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote:
> > > Add a property analogous to the vlenb CSR so that software can detect
> > > the vector length of each CPU prior to it being brought online.
> > > Currently software has to assume that the vector length read from the
> > > boot CPU applies to all possible CPUs. On T-Head CPUs implementing
> > > pre-ratification vector, reading the th.vlenb CSR may produce an ille=
gal
> > > instruction trap, so this property is required on such systems.
> > >=20
> > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > ---
> > >  Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >=20
> > > diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Doc=
umentation/devicetree/bindings/riscv/thead.yaml
> > > index 301912dcd290..5e578df36ac5 100644
> > > --- a/Documentation/devicetree/bindings/riscv/thead.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/thead.yaml
> > > @@ -28,6 +28,13 @@ properties:
> > >            - const: sipeed,lichee-module-4a
> > >            - const: thead,th1520
> > > =20
> > > +thead,vlenb:
> >=20
> > This needs to move back into cpus.yaml, this file documents root node
> > compatibles (boards and socs etc) and is not for CPUs. If you want to
> > restrict this to T-Head CPUs only, it must be done in cpus.yaml with
> > a conditional `if: not: ... then: properties: thead,vlenb: false`.
> >=20
> > Please test your bindings.
>=20
> Now that I know `make dt_binding_check` exists I will use that in the
> future!

And in this case dtbs_check would also complain about riscv,vlenb being
undocumented - and complain about thead,vlenb not being a permitted cpu
property either.

Thanks,
Conor.

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