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From: Frank Li <Frank.Li@nxp.com>
Date: Mon, 10 Jun 2024 16:46:18 -0400
Subject: [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2
 subsystem
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To: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, 
 Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, 
 Sascha Hauer <s.hauer@pengutronix.de>, 
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 Fabio Estevam <festevam@gmail.com>, Dong Aisheng <aisheng.dong@nxp.com>
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, 
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 =?utf-8?B?Ky9SVjBoNkx2eGR5MDNTaTlZU1R0bzl4TndWZ2FZSHJIdzcvQ0xsWGk4UGhT?=
 =?utf-8?B?RU04N0RHM3AzVnlaYlVTL3BBczlZTStobHFqRXh2TmxqdVdVZFVTb3dPL2lR?=
 =?utf-8?B?dWNCbnRJazBJcm51cDFvUHR5WjExdXZEL0ZJVGE4R09OV2ZIbzE4U3Z5dlR4?=
 =?utf-8?B?aWFHS21yZ1VPbkErclVlTHpGUmxBZC83dTMza1dERE9taVpDcUZQUjgyWFdl?=
 =?utf-8?B?dGh1VXFaaEVFVUExTXBFQTlOM0w5TFNuUGM4QkZHUm82NUk0UnRtWmplaUc0?=
 =?utf-8?B?Ym1ENWZoWGtOd3lndGJlOWFkYjRTR1YrN2dzUTdqVm9aRkVCaVdZYndPd3Ry?=
 =?utf-8?B?cFdhZzNTdEozd0ltcTk4QW5UeUVUSUFLTUNsdFBSalE0dWd6bUgxcDJ4OWR1?=
 =?utf-8?B?SXU1NkVCaTl2M0JuTS9BRTZROUttWlJ3UkhKY2RBY1czZjdmNGhWOTRXdUMy?=
 =?utf-8?B?d1RjbDZ3NC8vSkNJM2tTQ3BmcXh2NDBxYzUya0I5U3oxQkJBejVMUGlKQXpN?=
 =?utf-8?B?QkhsVDdQbWFXRHhLMm1tQzdWNEhlTTJOdjFxekt4N3hrQ2k1MkNYaERTZitj?=
 =?utf-8?B?Nmd3TjhMSm94TllrRlRjek8vWkIzZlN1SU5seEs5WjdhWXc0ZCttemN6TGN4?=
 =?utf-8?B?UTBrWXRKK3VFR3UvUVh3dTFSSlF0b1E1TW96Tjg4WnhENFA0Q1NyejBlSzQ4?=
 =?utf-8?B?SWE2K3JqU2FMcmk5YlVYUTlGRVVuOHFXdXpEaUpnYmtjOWhHaStFK1dLSllx?=
 =?utf-8?B?a3hVR3ZGZlQ0cTRZbU9jNnFoTzRsNGtFWDRUSmY3VWtRbjlCbWhIVWJlR2Ra?=
 =?utf-8?B?aG05Ym0zcEoxTnNuNCtaeWJFQ2JDT2dvandLODFMYi9pQ2Q0bkFIRHlFcWpH?=
 =?utf-8?B?bk5NTXFxbGYwcUFDMk9Fclh2NFZzaHp1dEhOTTdQUkZCSzRzSHdCTzIzcCtj?=
 =?utf-8?B?UHRnY0U4dmw0MzR4OG9uWXpOY1Jvdlp5cVptSVh4dVhMZ3poTWQyZHpDdThn?=
 =?utf-8?B?U2JiQ3ppcStYUkZxVTk5ZlA2NlNBcVZCcndyd0dYQnRxZEpjTGV5cThkNUJr?=
 =?utf-8?B?L3gzRS9PbjFIbGpsQTFiZU5ueWRoMUtLOUdGM2pRazFZMkk0WVAxakNWK3Ji?=
 =?utf-8?B?OHFrSWpuWXBsTDNzNWFrMFhXb0ljay9LZWJyOG9sb2RRTXpvRWdQUzRDNndW?=
 =?utf-8?B?Q0hjNG05WDZCMFpvYXB4UkQwRnVWWVE5a1ViRVJ5U0QyMVNGaGdMN1hNejZ4?=
 =?utf-8?B?U3Y2Wm5PNVdBcWNQd2NJQk9TdjJOdlBZekdXMmVMY0E0WHViL2dYV1BRNDAv?=
 =?utf-8?B?UGoyN0s5VFh2d3JLWmROQmtqUGY4RDNLZ3dUbVVtcmRtUnZjK2FLYm43VWpD?=
 =?utf-8?B?ZVdaOW8reWhUcmhlZ04vL1ZsSWF5akQ5eHFDMEQ1S1ZuWW8wZTBpU3AwMWpY?=
 =?utf-8?B?aGhScU5nemFFVDJYMGZiL2xOQnorUmJPZ1hzRVJZYm9lVXNPM2JaNStYMXh3?=
 =?utf-8?B?UEZLNkVENjNFaGsxdjRRVDN5T3hkQWxkZ2MyTjlORzdITVFPdmlOVndGLy8v?=
 =?utf-8?B?aU5HbXAveTIvaWxzZ2FWMW1sNXFpQUU3anExb0F4SGliVFBBeFBiZng1aTZs?=
 =?utf-8?B?aDRoV01WV0FadmI3Qm9rTVdTVFdOZWZMcURBVERwcWZnbmdacDJuNkMxeEpr?=
 =?utf-8?B?K1NWbHJZSzNqRzkyaE9xMXNDaElUNDlmeUJtTm1HblZGcUowVGxrZVoycHp2?=
 =?utf-8?B?UlNMV3VUZ3ROVzQ4RHhaUlJEQXp1dHo1YzI3cEphWXVCRzFxaWdxMVdzcHJx?=
 =?utf-8?B?T0hpdW9LWjJMWTZtK3pVNGNaMkFHU3FKNGV5N1JldHU0bnpGcFIxVDgzSzJz?=
 =?utf-8?B?SnVHSXNiQnl5RkFFejBWMnc3SVNONWE1a2hnQzV1QzVvcE5PWXNmYnd5aXlF?=
 =?utf-8?B?LzZUTEF1K3ZoQzc2NzZscVJWK1dUVS84enV5RmFWZVhwWTU3NVIwTUdiVkUv?=
 =?utf-8?B?TzF4S1hTVmlRK1d6UW1yeUFvdVBKYWcxTDlwWUVsM1ZlNURkVjdxSldaRGZ0?=
 =?utf-8?Q?TDbg=3D?=
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Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi |  63 +++++++++++++
 arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
 2 files changed, 177 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
new file mode 100644
index 0000000000000..55fd60446ad21
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds0_subsys: bus@56240000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56243000 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1>;
+	};
+
+	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5624300c 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_pwm_lpcg_clk",
+				     "mipi1_pwm_lpcg_ipg_clk",
+				     "mipi1_pwm_lpcg_32k_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+	};
+
+	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56243010 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_i2c0_lpcg_clk",
+				     "mipi1_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+	};
+
+	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x56244000 0x1000>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+		status = "disabled";
+	};
+
+	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x56246000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
new file mode 100644
index 0000000000000..12ae4f48e1e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds1_subsys: bus@57240000 {
+	compatible = "simple-bus";
+	interrupt-parent = <&irqsteer_lvds1>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+	irqsteer_lvds1: interrupt-controller@57240000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x57240000 0x1000>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+	};
+
+	lvds1_lis_lpcg: clock-controller@57243000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+	};
+
+	lvds1_pwm_lpcg: clock-controller@5724300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5724300c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_pwm_lpcg_clk",
+				     "lvds1_pwm_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+	};
+
+	lvds1_i2c0_lpcg: clock-controller@57243010 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243010 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_i2c0_lpcg_clk",
+				     "lvds1_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+	};
+
+	lvds1_i2c1_lpcg: clock-controller@57243014 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243014 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_i2c1_lpcg_clk",
+				     "lvds1_i2c1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+	};
+
+	pwm_lvds1: pwm@57244000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x57244000 0x1000>;
+		clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
+			 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+		status = "disabled";
+	};
+
+	i2c0_lvds1: i2c@57246000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x57246000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+			 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		status = "disabled";
+	};
+
+	i2c1_lvds1: i2c@57247000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x57247000 0x1000>;
+		interrupts = <9>;
+		clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
+			 <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		status = "disabled";
+	};
+};

-- 
2.34.1