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 <20240610-3cd1ba07c1b488a451dd7ddd@orel>
In-Reply-To: <20240610-3cd1ba07c1b488a451dd7ddd@orel>
From: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: Mon, 10 Jun 2024 14:11:23 -0700
Message-ID: <CAH2o1u6Yav1i=EUX-a4XY4OLtU5RvshHU5ffGE99mgSTrqmN2w@mail.gmail.com>
Subject: Re: [PATCH v7 6/7] iommu/riscv: Command and fault queue support
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, 
	Robin Murphy <robin.murphy@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, 
	Anup Patel <apatel@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, 
	Nick Kossifidis <mick@ics.forth.gr>, Sebastien Boeuf <seb@rivosinc.com>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, 
	iommu@lists.linux.dev, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, linux@rivosinc.com, 
	Lu Baolu <baolu.lu@linux.intel.com>, Zong Li <zong.li@sifive.com>
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On Mon, Jun 10, 2024 at 4:06=E2=80=AFAM Andrew Jones <ajones@ventanamicro.c=
om> wrote:
>
> On Wed, Jun 05, 2024 at 12:57:48PM GMT, Tomasz Jeznach wrote:
> ...
> > +static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu,
> > +                                struct riscv_iommu_queue *queue,
> > +                                size_t entry_size)
> > +{
> > +     unsigned int logsz;
> > +     u64 qb, rb;
> > +
> > +     /*
> > +      * Use WARL base register property to discover maximum allowed
> > +      * number of entries and optional fixed IO address for queue loca=
tion.
> > +      */
> > +     riscv_iommu_writeq(iommu, queue->qbr, RISCV_IOMMU_QUEUE_LOG2SZ_FI=
ELD);
> > +     qb =3D riscv_iommu_readq(iommu, queue->qbr);
> > +
> > +     /*
> > +      * Calculate and verify hardware supported queue length, as repor=
ted
> > +      * by the field LOG2SZ, where max queue length is equal to 2^(LOG=
2SZ + 1).
> > +      * Update queue size based on hardware supported value.
> > +      */
> > +     logsz =3D ilog2(queue->mask);
> > +     if (logsz > FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb))
> > +             logsz =3D FIELD_GET(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, qb);
> > +
> > +     /*
> > +      * Use WARL base register property to discover an optional fixed =
IO
> > +      * address for queue ring buffer location. Otherwise allocate con=
tiguous
> > +      * system memory.
> > +      */
> > +     if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) {
> > +             const size_t queue_size =3D entry_size << (logsz + 1);
> > +
> > +             queue->phys =3D ppn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIE=
LD, qb));
>
> Shouldn't this be something like
>
>   FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb) << PAGE_SHIFT
>
> ppn_to_phys() assumes the ppn it's converting to be shifted up by 10, but
> FIELD_GET has shifted it down to zero.
>

Good catch. It should be pfn_to_phys(). Fixed & verified on IOMMU with
queue ring buffers in fixed memory location.

Thanks,
- Tomasz

> Thanks,
> drew