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From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Tue, 11 Jun 2024 09:03:37 +0200
Message-ID: <CAMuHMdWY7SaL40oiFJ-wSA+x7NNZgE_0Wyj850QhbFz+yWwWTg@mail.gmail.com>
Subject: Re: [PATCH 3/4] clk: renesas: Add RZ/V2H CPG core wrapper driver
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, 
	Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Philipp Zabel <p.zabel@pengutronix.de>, Magnus Damm <magnus.damm@gmail.com>, 
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Prabhakar,

On Tue, Jun 11, 2024 at 12:03=E2=80=AFAM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Jun 4, 2024 at 5:01=E2=80=AFPM Geert Uytterhoeven <geert@linux-m6=
8k.org> wrote:
> > On Fri, May 24, 2024 at 10:29=E2=80=AFAM Prabhakar <prabhakar.csengg@gm=
ail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add CPG core helper wrapper driver for RZ/V2H SoC.
> >
> > What is a "core helper wrapper"? ;-)
> >
> As this file basically uses core API for clock and reset, I worded the
> commit as such.
>
> > Looking at the structure, this looks like a family-specific clock drive=
r?
> Yes, as the CPG on RZ/V2H varies quite a bit compared to RZ/G2L I have
> introduced a family-specific clock driver
>
> > Will there be more RZ/V2H-alike SoCs?
> >
> I'm not sure about it tbh!

OK, I see we did the same when introducing RZ/G2L support.

> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.h

> > > +/**
> > > + * struct rzv2h_cpg_info - SoC-specific CPG Description
> > > + *
> > > + * @core_clks: Array of Core Clock definitions
> > > + * @num_core_clks: Number of entries in core_clks[]
> > > + * @num_total_core_clks: Total number of Core Clocks (exported + int=
ernal)
> > > + *
> > > + * @mod_clks: Array of Module Clock definitions
> > > + * @num_mod_clks: Number of entries in mod_clks[]
> > > + * @num_hw_mod_clks: Number of Module Clocks supported by the hardwa=
re
> > > + *
> > > + * @resets: Array of Module Reset definitions
> > > + * @num_resets: Number of entries in resets[]
> > > + *
> > > + * @crit_mod_clks: Array with Module Clock IDs of critical clocks th=
at
> > > + *                 should not be disabled without a knowledgeable dr=
iver
> > > + * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> > > + * @pll_get_clk1_offset: Function pointer to get PLL CLK1 offset
> > > + * @pll_get_clk2_offset: Function pointer to get PLL CLK2 offset
> > > + */
> > > +struct rzv2h_cpg_info {
> >
> > > +       /* function pointers for PLL information */
> > > +       int (*pll_get_clk1_offset)(int clk);
> > > +       int (*pll_get_clk2_offset)(int clk);
> >
> > Why are these function pointers?

I meant "... and not pointer/len pairs?".

> To get the offsets for PLL CLK1/2. But I plan to drop these and get
> the offset from conf instead.

OK

Gr{oetje,eeting}s,

                        Geert

--=20
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k=
.org

In personal conversations with technical people, I call myself a hacker. Bu=
t
when I'm talking to journalists I just say "programmer" or something like t=
hat.
                                -- Linus Torvalds