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Date: Tue, 11 Jun 2024 10:45:37 +0200
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>,
	=?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= <zajec5@gmail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Florian Fainelli <florian.fainelli@broadcom.com>,
	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>,
	linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 1/4] mips: bmips: rework and cache CBR addr handling
Message-ID: <ZmgOsZ+yvfOUDZoq@alpha.franken.de>
References: <20240511130349.23409-1-ansuelsmth@gmail.com>
 <20240511130349.23409-2-ansuelsmth@gmail.com>
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In-Reply-To: <20240511130349.23409-2-ansuelsmth@gmail.com>

On Sat, May 11, 2024 at 03:03:45PM +0200, Christian Marangi wrote:
> diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
> index 99a1ba5394e0..49fe4c535161 100644
> --- a/arch/mips/bcm47xx/prom.c
> +++ b/arch/mips/bcm47xx/prom.c
> @@ -109,6 +109,8 @@ static __init void prom_init_mem(void)
>  
>  void __init prom_init(void)
>  {
> +	/* Cache CBR addr before CPU/DMA setup */
> +	bmips_cbr_addr = BMIPS_GET_CBR();
>  	prom_init_mem();
>  	setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
>  }

doesn't compile for me, probably missing and #include

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]