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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, Dong Aisheng <aisheng.dong@nxp.com>, linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li <Frank.Li@nxp.com>, Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v2 3/9] arm64: dts: imx8: add basic mipi subsystem
Date: Tue, 11 Jun 2024 13:14:20 +0200
Message-ID: <13535816.uLZWGnKmhe@steina-w>
Organization: TQ-Systems GmbH
In-Reply-To: <20240610-imx8qm-dts-usb-v2-3-788417116fb1@nxp.com>
References: <20240610-imx8qm-dts-usb-v2-0-788417116fb1@nxp.com> <20240610-imx8qm-dts-usb-v2-3-788417116fb1@nxp.com>
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Am Montag, 10. Juni 2024, 22:46:20 CEST schrieb Frank Li:
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> ********************
>=20
> Add basic mipi subsystem for imx8qm and imx8qxp.
>=20
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++=
++++++
>  arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++=
++++++
>  2 files changed, 276 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm6=
4/boot/dts/freescale/imx8-ss-mipi0.dtsi
> new file mode 100644
> index 0000000000000..6b56315e8c434
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi0_subsys: bus@56220000 {
> +	compatible =3D "simple-bus";
> +	interrupt-parent =3D <&irqsteer_mipi0>;
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	ranges =3D <0x56220000 0x0 0x56220000 0x10000>;
> +
> +	irqsteer_mipi0: interrupt-controller@56220000 {
> +		compatible =3D "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
> +		reg =3D <0x56220000 0x1000>;
> +		interrupts =3D <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent =3D <&gic>;
> +		#interrupt-cells =3D <1>;
> +		clocks =3D <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> +		clock-names =3D "ipg";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0>;
> +		fsl,channel =3D <0>;
> +		fsl,num-irqs =3D <32>;
> +	};
> +
> +	mipi0_lis_lpcg: clock-controller@56223000 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x56223000 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;

That's LPCG_DI_LVDS_LPCG_0 for imx8qxp, no? So clock-indices and
clock-output-names should be split similar to patch.

> +		clock-output-names =3D "mipi0_lis_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0>;
> +	};
> +
> +	mipi0_pwm_lpcg: clock-controller@5622300c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5622300c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> +			 <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names =3D "mipi0_pwm_lpcg_clk",
> +				     "mipi0_pwm_lpcg_ipg_clk";

That's LPCG_DI_MIPI_LPCG_12, no? imx8qm RM Rev 0 just lists one clock.
Also it's different on imx8qxp.

> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_PWM_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x56223014 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;

Just 0 instead of IMX_LPCG_CLK_0.

> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c0_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x56223018 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c0_lpcg_ipg_s_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5622301c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c0_lpcg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x56223024 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c1_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5622302c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c1_lpcg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x56223028 0x4>;

Order nodes by base address please.

> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi0_i2c1_lpcg_ipg_s_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	pwm_mipi0: pwm@56224000 {
> +		compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg =3D <0x56224000 0x1000>;
> +		clocks =3D <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> +			 <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;

I don't think that's correct. IMX_LPCG_CLK_4 evaluates to 16.
'mipi0_pwm_lpcg' only has 2 clocks, so you should use just '1' and '0'.

> +		clock-names =3D "ipg", "per";
> +		assigned-clocks =3D <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates =3D <24000000>;
> +		#pwm-cells =3D <3>;
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_PWM_0>;
> +		status =3D "disabled";
> +	};
> +
> +	i2c0_mipi0: i2c@56226000 {
> +		compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg =3D <0x56226000 0x1000>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		interrupts =3D <8>;
> +		clocks =3D <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> +			 <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;

Just use 0 instead of IMX_LPCG_CLK_0.

> +		clock-names =3D "per", "ipg";
> +		assigned-clocks =3D <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> +		assigned-clock-rates =3D <24000000>;
> +		power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +		status =3D "disabled";
> +	};
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm6=
4/boot/dts/freescale/imx8-ss-mipi1.dtsi
> new file mode 100644
> index 0000000000000..5b1f08e412b24
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi

This is only for imx8qm, no?

It maybe makes sense to rename this file to imx8qm-ss-mipi1.dtsi

Best regards,
Alexander

> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi1_subsys: bus@57220000 {
> +	compatible =3D "simple-bus";
> +	interrupt-parent =3D <&irqsteer_mipi1>;
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	ranges =3D <0x57220000 0x0 0x57220000 0x10000>;
> +
> +	irqsteer_mipi1: interrupt-controller@57220000 {
> +		compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg =3D <0x57220000 0x1000>;
> +		interrupts =3D <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent =3D <&gic>;
> +		#interrupt-cells =3D <1>;
> +		clocks =3D <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> +		clock-names =3D "ipg";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1>;
> +		fsl,channel =3D <0>;
> +		fsl,num-irqs =3D <32>;
> +	};
> +
> +	mipi1_lis_lpcg: clock-controller@57223000 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x57223000 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_lis_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1>;
> +	};
> +
> +	mipi1_pwm_lpcg: clock-controller@5722300c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5722300c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> +			 <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names =3D "mipi1_pwm_lpcg_clk",
> +				     "mipi1_pwm_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5722301c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c0_lpcg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x57223014 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c0_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x57223018 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c0_lpcg_ipg_s_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x57223024 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c1_lpcg_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x57223028 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&dsi_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c1_lpcg_ipg_s_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x5722302c 0x4>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>;
> +		clock-output-names =3D "mipi1_i2c1_lpcg_clk";
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	pwm_mipi1: pwm@57224000 {
> +		compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg =3D <0x57224000 0x1000>;
> +		clocks =3D <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> +			 <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> +		clock-names =3D "ipg", "per";
> +		assigned-clocks =3D <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates =3D <24000000>;
> +		#pwm-cells =3D <3>;
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +		status =3D "disabled";
> +	};
> +
> +	i2c0_mipi1: i2c@57226000 {
> +		compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg =3D <0x57226000 0x1000>;
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		interrupts =3D <8>;
> +		interrupt-parent =3D <&irqsteer_mipi1>;
> +		clocks =3D <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> +			 <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> +		clock-names =3D "per", "ipg";
> +		assigned-clocks =3D <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> +		assigned-clock-rates =3D <24000000>;
> +		power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +		status =3D "disabled";
> +	};
> +};
>=20
>=20


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