Received-SPF: pass (google.com: domain of linux-kernel+bounces-210241-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1;
Date: Tue, 11 Jun 2024 17:24:17 +0100
From: Conor Dooley <conor@kernel.org>
To: Minda Chen <minda.chen@starfivetech.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v1] riscv: dts: starfive: add PCIe dts configuration for
 JH7110
Message-ID: <20240611-irk-hypocrite-a53e98e6c394@spud>
References: <20240611015200.40996-1-minda.chen@starfivetech.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
	protocol="application/pgp-signature"; boundary="wzZC5MCZUi+ZMG8A"
Content-Disposition: inline
In-Reply-To: <20240611015200.40996-1-minda.chen@starfivetech.com>


--wzZC5MCZUi+ZMG8A
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote:
> Add PCIe dts configuraion for JH7110 SoC platform.
>=20
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../boot/dts/starfive/jh7110-common.dtsi      | 64 ++++++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 86 +++++++++++++++++++
>  2 files changed, 150 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv=
/boot/dts/starfive/jh7110-common.dtsi
> index 8ff6ea64f048..1da7379f4e08 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -294,6 +294,22 @@
>  	status =3D "okay";
>  };
> =20
> +&pcie0 {
> +	perst-gpios =3D <&sysgpio 26 GPIO_ACTIVE_LOW>;
> +	phys =3D <&pciephy0>;
> +	pinctrl-names =3D "default";
> +	pinctrl-0 =3D <&pcie0_pins>;
> +	status =3D "okay";
> +};
> +
> +&pcie1 {
> +	perst-gpios =3D <&sysgpio 28 GPIO_ACTIVE_LOW>;
> +	phys =3D <&pciephy1>;
> +	pinctrl-names =3D "default";
> +	pinctrl-0 =3D <&pcie1_pins>;
> +	status =3D "okay";
> +};

Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports
exposed? I assume if one does, all does, since they're basically
identical?

--wzZC5MCZUi+ZMG8A
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZmh6MQAKCRB4tDGHoIJi
0v1MAP9PTX9Hu0d+NafLeM2JG8n5oxSljJKr6Q/CDKPbUeaOcgEAxScFlExYbnQb
F951+zWbwytmbr3baByHSjGl6D2Cigg=
=ds5C
-----END PGP SIGNATURE-----

--wzZC5MCZUi+ZMG8A--