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AJvYcCVJZvn2LgVXnYtTR5wVcbxQbIVM/JrjWGj3toXePjRveeOuczamal3VarbGBb5pJjFxPrraNtG/tSI2wTA9TSVtKt/qq1mUVfIQVtKC X-Gm-Message-State: AOJu0YyzLSgJKLZEjbvufc6V1w52kCCBwPoTkWLgnVpqHET9NlHKdv1o w6J3VhF9UesoPnWmstt52E0qaECSuIFtvJtadpXKCQIrTZoLBb0pWB1yJx0MCaZuPVjXV7SUfuq iCM6vuJkEFIAAtYt5w5Kj0z9Yr9+mcU5ops4xJA== X-Received: by 2002:a25:ab24:0:b0:dfa:ff7e:d410 with SMTP id 3f1490d57ef6-dfaff7ed6f5mr11899278276.40.1718127591425; Tue, 11 Jun 2024 10:39:51 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240607-trimmer-pummel-b452ed15e103@spud> <20240607155704.GB1242@pendragon.ideasonboard.com> <20240607-celibacy-contend-c4a6be15804b@spud> <20240610-wolverine-hanky-37cc8c409958@wendy> In-Reply-To: <20240610-wolverine-hanky-37cc8c409958@wendy> From: Dave Stevenson Date: Tue, 11 Jun 2024 18:39:35 +0100 Message-ID: Subject: Re: [PATCH v1] media: i2c: imx219: fix msr access command sequence To: Conor Dooley Cc: Conor Dooley , Laurent Pinchart , linux-media@vger.kernel.org, Sakari Ailus , Mauro Carvalho Chehab , Adam Ford , Andrey Konovalov , linux-kernel@vger.kernel.org, Naushir Patuck Content-Type: text/plain; charset="UTF-8" Hi Conor On Mon, 10 Jun 2024 at 08:32, Conor Dooley wrote: > > On Fri, Jun 07, 2024 at 06:55:01PM +0100, Conor Dooley wrote: > > On Fri, Jun 07, 2024 at 06:29:49PM +0100, Dave Stevenson wrote: > > > > > > > --- > > > > > I got the report of this third hand, I don't have a device and can't > > > > > test this. I do wonder why the RPis get away with the sequence that > > > > > seemingly doesn't work for the guy that reported this to me. My theory > > > > > is either that they noticed the sequence was wrong while adding some > > > > > other MSR access that is needed on this board while either cross > > > > > checking the values written or because the other MSR accesses didn't > > > > > take effect. > > > > > > Did the change fix it for the reporter? We're using the driver with no > > > changes to the register settings cf mainline. > > > Why it works on the Pi but not on a Microchip board is likely to be > > > something quite subtle. > > > > I've asked, maybe it turns out to just be the first of my suggestions, > > and they noticed it was not matching in passing. > > Apparently it was the latter & they did need to fix the sequence to be > able to write the MSRs. Fair enough. > > They did introduce two > > additional MSR accesses, both outside of the range documented in the > > datasheets I could find online. They did have explanations for what those > > undocumented MSRs did (0x5040 and 0x5041) in the mail I got, but given > > it's third hand info to me, I dunno if we have the datasheet etc. I'll > > try to find out some more next week. > > Seemingly what those two additional MSRs do is under NDA so I would have > no way of justifying a patch to add them or the devicetree property > required to know whether or not the additional MSR writes is needed. :) NDAs can be a real pain sometimes. I'm happy with the patch though, and it doesn't stop anything else working on the Pi. Reviewed-by: Dave Stevenson Tested-by: Dave Stevenson