Received: by 2002:ab2:69cc:0:b0:1fd:c486:4f03 with SMTP id n12csp515318lqp; Tue, 11 Jun 2024 10:49:16 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCUeQKsB4lKdnmHgDm2Acg+hnqhiH7l4Iwip64fZoYWeWySSyyqI4OhdZNA75b3dAohA+CJBctnk+bo9t/x9zysKkp2etSN5KEAyuW80xg== X-Google-Smtp-Source: AGHT+IHwirBSg2pd1omNf0r8paAEwaqMNOXvyzqW+WfY95LtFgdo7IarqKe4ZOtbN0LeWRvUMxJ/ X-Received: by 2002:a50:ab0d:0:b0:572:4fc3:3a28 with SMTP id 4fb4d7f45d1cf-57c5092fbbfmr7657619a12.23.1718128156285; Tue, 11 Jun 2024 10:49:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1718128156; cv=pass; d=google.com; s=arc-20160816; b=0fTft1ND9PXDrDntXFA0G4IWjyw3w/vfj5khs94ZEzw11KdSQirtfJdX+QYYLYNYIp j/KrvioP7rnQVKq5w5WDQTe8vYwh7Rb7vPwQp/+UrLdosmAw3U16scaUG/BguJeIks9q CKSMjm/FhU4OsFj50/5+IlP4oPy3A86hry31Ez1n2q3ClIh/C32myP5miUSDtDH/Pmv3 u1cOFYBaCAS+lOe8tEJVD3vrHonwQ6dY2283rlya+i1UOyxuGMcAZdezOwZElOVfSYX2 0VhnZQxkXM403DYJUEsOeWc5G0Zsw8SauqD9KOtbl28qSKG/pUjEnKVBrcCm+Fu0v7Wl WDqA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:message-id:subject:cc :to:from:date; bh=xoU4bus5Y4kIl3eNA453GkViawRptQhmd5JkGHvADms=; fh=pRn1dCCCDMYFjvWA3G+g8ETmqk49SnxJqcrd5w2g+yU=; b=XwZVM1xId+LGHOle5s5aWaQvZ22AbFzpBiLcbtPVqACEyTmiDRQu4kG9XJNJjaS1hi 16slYuX+LtlQXNC2AR/VOsW/gy2Ejh8mYA8ey9d//Sm4txFyA07id3j/EDgKr5swXGck MFlzDQ/jdS0QDKi8xRhg6E/rL6GeeX88nGFWPCGkN9zgEY+hEBTnLHN8DqxltAeo5K7g DYSfil6zqQSgY0+RaSwrsoaqr0gJOfMkV6P5kY5Po1JEi+V89aynY2VUi/ea9FuWbO9f mFE19aNItSS1Q5TmAjvfr3nZARZYAQIxQcd/7S6TB/Pz6EkeOaIOh8T7izL04irZBO0w Eu2w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-210353-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-210353-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-57c818de42esi2363281a12.81.2024.06.11.10.49.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 10:49:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-210353-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-210353-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-210353-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 085001F21837 for ; Tue, 11 Jun 2024 17:49:16 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7295C60BBE; Tue, 11 Jun 2024 17:48:59 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4873B5CDE9; Tue, 11 Jun 2024 17:48:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718128138; cv=none; b=GRiHMaBHDKJd1KypLmoT3mCk/dxzv7EwlqdRptBLuzBiuPbrPK5z/+4pl+xPDtZpALTsaxoBYXMPS2ENavLTnOk9KAkRdvbQSIKHQ3FonLNz4y5711sS4kFeId6edqIa+AQEn3ia//EMXTLl88PV3t7XU+qCE+z4mPyL1Xo+BiI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718128138; c=relaxed/simple; bh=6PB6r+2ivy1DqOODJ6xPwma2D1oQ5gkONrmouW8ygT4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=OwuYjuWzh9U5S6SHNPe6oQ0Q0x+0OZoADLOZMLuHQtQTXQBGnYBjmbgBANfNvLCp6gmVrkXhs6hu7bduE1CJ+HaFl1lhjk8ibw6oAI5HqjoYKiIphlgcRrjyVPht+R1PMxWvypx/4EZ3nkYyDve3HKx6v/t8wVu5wVuJeCoAxrA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD344152B; Tue, 11 Jun 2024 10:49:19 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 06D643F73B; Tue, 11 Jun 2024 10:48:52 -0700 (PDT) Date: Tue, 11 Jun 2024 18:48:47 +0100 From: Mark Rutland To: Linus Torvalds Cc: Peter Anvin , Ingo Molnar , Borislav Petkov , Thomas Gleixner , Rasmus Villemoes , Josh Poimboeuf , Catalin Marinas , Will Deacon , Linux Kernel Mailing List , the arch/x86 maintainers , linux-arm-kernel@lists.infradead.org, linux-arch Subject: Re: [PATCH 4/7] arm64: add 'runtime constant' support Message-ID: References: <20240610204821.230388-1-torvalds@linux-foundation.org> <20240610204821.230388-5-torvalds@linux-foundation.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jun 11, 2024 at 09:56:17AM -0700, Linus Torvalds wrote: > On Tue, 11 Jun 2024 at 07:29, Mark Rutland wrote: > > > > Do we expect to use this more widely? If this only really matters for > > d_hash() it might be better to handle this via the alternatives > > framework with callbacks and avoid the need for new infrastructure. > > Hmm. The notion of a callback for alternatives is intriguing and would > be very generic, but we don't have anything like that right now. > > Is anybody willing to implement something like that? Because while I > like the idea, it sounds like a much bigger change. Fair enough if that's a pain on x86, but we already have them on arm64, and hence using them is a smaller change there. We already have a couple of cases which uses MOVZ;MOVK;MOVK;MOVK sequence, e.g. // in __invalidate_icache_max_range() asm volatile(ALTERNATIVE_CB("movz %0, #0\n" "movk %0, #0, lsl #16\n" "movk %0, #0, lsl #32\n" "movk %0, #0, lsl #48\n", ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0) : "=r" (ctr)); ... which is patched via the callback: void kvm_compute_final_ctr_el0(struct alt_instr *alt, __le32 *origptr, __le32 *updptr, int nr_inst) { generate_mov_q(read_sanitised_ftr_reg(SYS_CTR_EL0), origptr, updptr, nr_inst); } ... where the generate_mov_q() helper does the actual instruction generation. So if we only care about a few specific constants, we could give them their own callbacks, like kvm_compute_final_ctr_el0() above. [...] > > We have some helpers for instruction manipulation, and we can use > > aarch64_insn_encode_immediate() here, e.g. > > > > #include > > > > static inline void __runtime_fixup_16(__le32 *p, unsigned int val) > > { > > u32 insn = le32_to_cpu(*p); > > insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, val); > > *p = cpu_to_le32(insn); > > } > > Ugh. I did that, and then noticed that it makes the generated code > about ten times bigger. > > That interface looks positively broken. > > There is absolutely nobody who actually wants a dynamic argument, so > it would have made both the callers and the implementation *much* > simpler had the "AARCH64_INSN_IMM_16" been encoded in the function > name the way I did it for my instruction rewriting. > > It would have made the use of it simpler, it would have avoided all > the "switch (type)" garbage, and it would have made it all generate > much better code. Oh, completely agreed. FWIW, I have better versions sat in my arm64/insn/rework branch, but I haven't had the time to get all the rest of the insn framework cleanup sorted: https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?h=arm64/insn/rework&id=9cf0ec088c9d5324c60933bf3924176fea0a4d0b I can go prioritise getting that bit out if it'd help, or I can clean this up later. Those allow the compiler to do much better, including compile-time (or runtime) checks that immediates fit. For example: void encode_imm16(__le32 *p, u16 imm) { u32 insn = le32_to_cpu(*p); // Would warn if 'imm' were u32. // As u16 always fits, no warning BUILD_BUG_ON(!aarch64_insn_try_encode_unsigned_imm16(&insn, imm)); *p = cpu_to_le32(insn); } ... compiles to: : ldr w2, [x0] bfi w2, w1, #5, #16 str w2, [x0] ret ... which I think is what you want? > So I did that change you suggested, and then undid it again. > > Because that whole aarch64_insn_encode_immediate() thing is an > abomination, and should be burned at the stake. It's misdesigned in > the *worst* possible way. > > And no, this code isn't performance-critical, but I have some taste, > and the code I write will not be using that garbage. Fair enough. Mark.