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AJvYcCUS1mg9AXb+jNNtrDZSCIBsZ4VRwd7cC6q1ydM1Yh4QA0QLoeS5QDt+v3GsD55tSyHQElGJJl+pmvt09gkxZuJTc1I+n+E7uxUspfNZ X-Gm-Message-State: AOJu0Yyd5/6NNeGySnDewIJBAdBDRecLH6EoDkfp5Il5Z4f9+wkTQIJ5 qDYWj1sivAvxaoVJm6u6q+Mb0xqDkmu+fYncdRsubba0148+FMShIYhATo+Fh3YoDgH0Ld+MQav F7dOUwjzoP+hC8Df0fIdgkGtdx7OIf2OWLuc3vg== X-Received: by 2002:a50:9e2e:0:b0:57c:ad96:14c8 with SMTP id 4fb4d7f45d1cf-57cad961876mr323057a12.23.1718179390979; Wed, 12 Jun 2024 01:03:10 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org> <20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org> In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org> From: Peter Griffin Date: Wed, 12 Jun 2024 09:02:57 +0100 Message-ID: Subject: Re: [PATCH 1/5] phy: exynos5-usbdrd: uniform order of register bit macros To: =?UTF-8?Q?Andr=C3=A9_Draszik?= Cc: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Sam Protsenko , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Andr=C3=A9, On Tue, 7 May 2024 at 15:14, Andr=C3=A9 Draszik = wrote: > > Most of the macros are ordered high -> low, but there are some > outliers. > > Order them all uniformly from high to low. This will allow adding > additional register (field) definitions in a consistent way. > > While at it, also remove some extra empty lines to group register bit > field definitions together with the relevant register. This makes the > registers easier to distinguish visually. > > No functional change. > > Signed-off-by: Andr=C3=A9 Draszik > --- Reviewed-by: Peter Griffin regards, Peter [..]