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Wed, 12 Jun 2024 04:54:35 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:30 +0100 Subject: [PATCH v2 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240612-mips-clks-v2-3-a57e6f49f3db@flygoat.com> References: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com> To: Thomas Bogendoerfer , Serge Semin , Daniel Lezcano , Thomas Gleixner Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=723; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=/1HBI8X5gA92dWi6gRt06ZHjuNwe7f7CMITzKjoFsHY=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMJPfQo4IxfadkbvfcyxQ1OWl01tm1vmmCi4nUdoVCW aHbWy91lLIwiHExyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwESyKhn+p7NGbLB9sfVH1fP5 8bzl31W89Fs8r21qtWa6HsMlYqkyn+F/6N058VPq/pw+fNh5y50H0fMTKrurX8+9vy9o1sygPZf bmAE= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 csrc-r4k suffers from SMP synchronization overhead. Select HAVE_UNSTABLE_SCHED_CLOCK to workaround drift between the CPUs on the system. HAVE_UNSTABLE_SCHED_CLOCK requires cmpxchg64, so enable it for 64 bits only. Signed-off-by: Jiaxun Yang --- v2: Depends on SMP as well --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f1aa1bf11166..656df5d4097d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1083,6 +1083,7 @@ config CSRC_IOASIC config CSRC_R4K select CLOCKSOURCE_WATCHDOG if CPU_FREQ + select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT bool config CSRC_SB1250 -- 2.43.0