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Wed, 12 Jun 2024 05:53:36 -0400 (EDT) From: Jiaxun Yang Date: Wed, 12 Jun 2024 10:53:31 +0100 Subject: [PATCH v2 3/4] MIPS: Select ARCH_SUPPORTS_ATOMIC_RMW when possible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240612-mips-llsc-v2-3-a42bd5562bdb@flygoat.com> References: <20240612-mips-llsc-v2-0-a42bd5562bdb@flygoat.com> In-Reply-To: <20240612-mips-llsc-v2-0-a42bd5562bdb@flygoat.com> To: Thomas Bogendoerfer Cc: Jonas Gorski , "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=698; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=fCm2taCoWVcHA6K66WtthUu/hvdqStZPGA1RkuysGM0=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrTMAlmfi/9cPXnmJHUfLGxUkre78HA5m9/vEyn7IiYLO 5sFSc7tKGVhEONikBVTZAkRUOrb0HhxwfUHWX9g5rAygQxh4OIUgImsDmX4zcq0arV6h6aZdE7W S6H+Qyu/scq8P8zdaxfAefA6e/ciY4b/qXsXtYRrvlRd2ZI3ISz7/qvaXy2z045pXXvBH1j2zsq CGQA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Select ARCH_SUPPORTS_ATOMIC_RMW when we are certain that our CPU have LLSC support. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 50260a7e9b54..e83036580a47 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,6 +23,7 @@ config MIPS select ARCH_USE_MEMTEST select ARCH_USE_QUEUED_RWLOCKS select ARCH_USE_QUEUED_SPINLOCKS + select ARCH_SUPPORTS_ATOMIC_RMW if CPU_HAS_LLSC select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_IPC_PARSE_VERSION -- 2.43.0