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Date: Wed, 12 Jun 2024 12:15:47 +0100
From: Conor Dooley <conor@kernel.org>
To: Minda Chen <minda.chen@starfivetech.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: Re : [PATCH v1] riscv: dts: starfive: add PCIe dts configuration
 for JH7110
Message-ID: <20240612-italicize-cultural-a10b8a387520@spud>
References: <20240611015200.40996-1-minda.chen@starfivetech.com>
 <20240611-irk-hypocrite-a53e98e6c394@spud>
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On Wed, Jun 12, 2024 at 01:48:55AM +0000, Minda Chen wrote:
>=20
>=20
> >=20
> > On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote:
> > > Add PCIe dts configuraion for JH7110 SoC platform.
> > >
> > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > >  .../boot/dts/starfive/jh7110-common.dtsi      | 64 ++++++++++++++
> > >  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 86 +++++++++++++++++=
++
> > >  2 files changed, 150 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > index 8ff6ea64f048..1da7379f4e08 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > > @@ -294,6 +294,22 @@
> > >  	status =3D "okay";
> > >  };
> > >
> > > +&pcie0 {
> > > +	perst-gpios =3D <&sysgpio 26 GPIO_ACTIVE_LOW>;
> > > +	phys =3D <&pciephy0>;
> > > +	pinctrl-names =3D "default";
> > > +	pinctrl-0 =3D <&pcie0_pins>;
> > > +	status =3D "okay";
> > > +};
> > > +
> > > +&pcie1 {
> > > +	perst-gpios =3D <&sysgpio 28 GPIO_ACTIVE_LOW>;
> > > +	phys =3D <&pciephy1>;
> > > +	pinctrl-names =3D "default";
> > > +	pinctrl-0 =3D <&pcie1_pins>;
> > > +	status =3D "okay";
> > > +};
> >=20
> > Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports expo=
sed? I
> > assume if one does, all does, since they're basically identical?
>=20
> Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0,=
 PCIe1 pins are the same.

This patch adds both PCIe instances for the Star64 though, since that
also includes jh7110-common.dtsi. I think you need to enable these in
the board dts files instead?

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