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Date: Wed, 12 Jun 2024 09:29:25 -0300
From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
	thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v8 5/6] iommu/arm-smmu-v3: Add in-kernel support for
 NVIDIA Tegra241 (Grace) CMDQV
Message-ID: <20240612122925.GA19897@nvidia.com>
References: <cover.1716883239.git.nicolinc@nvidia.com>
 <e7dab374702aaac8dc81b95ddf89c94befe409dd.1716883239.git.nicolinc@nvidia.com>
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On Tue, May 28, 2024 at 01:09:53AM -0700, Nicolin Chen wrote:

> +/* MMIO helpers */
> +#define REG_CMDQV(_cmdqv, _regname) \
> +	((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> +#define REG_VINTF(_vintf, _regname) \
> +	((_vintf)->base + TEGRA241_VINTF_##_regname)
> +#define REG_VCMDQ_PAGE0(_vcmdq, _regname) \
> +	((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> +#define REG_VCMDQ_PAGE1(_vcmdq, _regname) \
> +	((_vcmdq)->page1 + TEGRA241_VCMDQ_##_regname)

This looks OK now

I didn't see any thing else really important in this patch

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

> +static inline int cmdqv_write_config(struct tegra241_cmdqv *cmdqv, u32 regval)
> +{
> +	return tegra241_cmdqv_write_config(cmdqv,
> +					   cmdqv->base + TEGRA241_CMDQV_CONFIG,
> +					   cmdqv->base + TEGRA241_CMDQV_STATUS,
> +					   regval, "CMDQV: ", NULL);

However it would be good to go and fix these case to use the REG_xx
macros, I noticed several.

Jason