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charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Thomas, Martin, On Tue, Jun 11, 2024 at 04:12:18PM +0200, Thomas Bogendoerfer wrote: > On Fri, Jun 07, 2024 at 11:04:00AM +0200, Martin Schiller wrote: > > Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not > > only switched to the gpiod API, but also inverted / changed the polarity > > of the GPIO. > > > > According to the PCI specification, the RST# pin is an active-low > > signal. However, most of the device trees that have been widely used for > > a long time (mainly in the openWrt project) define this GPIO as > > active-high and the old driver code inverted the signal internally. > > > > Apparently there are actually boards where the reset gpio must be > > operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH > > flag for initialization. Instead, we must explicitly set the gpio to > > value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that > > may have been set. > > > > In order to remain compatible with all these existing device trees, we > > should therefore keep the logic as it was before the commit. > > > > Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") > > Cc: stable@vger.kernel.org > > Signed-off-by: Martin Schiller > > --- > > arch/mips/pci/pci-lantiq.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > applied to mips-fixes The patch is unfortunately also wrong as it will break any board that actually has correct polarity annotation. I will prepare a quirk for drivers/gpio/gpiolib-of.c to force the polarity to low for this GPIO. Thanks. -- Dmitry