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Date: Wed, 12 Jun 2024 17:30:36 +0100
From: Conor Dooley <conor@kernel.org>
To: Alisa-Dariana Roman <alisadariana@gmail.com>
Cc: Alisa-Dariana Roman <alisa.roman@analog.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Michael Hennerich <michael.hennerich@analog.com>,
	linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Alexandru Tachici <alexandru.tachici@analog.com>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Jonathan Cameron <jic23@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: iio: adc: ad7192: Fix clock config
Message-ID: <20240612-daylong-unnamable-c6f3aa60c8e3@spud>
References: <20240612141637.175709-1-alisa.roman@analog.com>
 <20240612141637.175709-2-alisa.roman@analog.com>
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On Wed, Jun 12, 2024 at 05:16:36PM +0300, Alisa-Dariana Roman wrote:
> There are actually 4 configuration modes of clock source for AD719X
> devices. Either a crystal can be attached externally between MCLK1 and
> MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
> pin. The other 2 modes make use of the 4.92MHz internal clock.
>=20
> The presence of an external clock is optional, not required. When
> absent, internal clock of the device is used.
>=20
> Fixes: f7356e47032c ("dt-bindings: iio: adc: ad7192: Add binding document=
ation for AD7192")
> Signed-off-by: Alisa-Dariana Roman <alisa.roman@analog.com>
> ---
>  .../devicetree/bindings/iio/adc/adi,ad7192.yaml    | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>=20
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/=
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> index a03da9489ed9..3ae2f860d24c 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> @@ -39,11 +39,15 @@ properties:
> =20
>    clocks:
>      maxItems: 1
> -    description: phandle to the master clock (mclk)
> +    description: |
> +      Optionally, either a crystal can be attached externally between MC=
LK1 and
> +      MCLK2 pins, or an external CMOS-compatible clock can drive the MCL=
K2
> +      pin. If absent, internal 4.92MHz clock is used.
> =20
>    clock-names:
> -    items:
> -      - const: mclk
> +    enum:
> +      - xtal
> +      - mclk

Nothing in this commit message explains why "mclk" is not a suitable
name for either of the two configurations.

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