Received-SPF: pass (google.com: domain of linux-kernel+bounces-212120-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
 216.228.118.232 as permitted sender) receiver=protection.outlook.com;
 client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C
Date: Wed, 12 Jun 2024 11:50:09 -0700
From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
CC: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>,
	<thierry.reding@gmail.com>, <vdumpa@nvidia.com>, <jonathanh@nvidia.com>,
	<linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
	<linux-arm-kernel@lists.infradead.org>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v8 5/6] iommu/arm-smmu-v3: Add in-kernel support for
 NVIDIA Tegra241 (Grace) CMDQV
Message-ID: <Zmnt4RL+RcDiwurc@Asurada-Nvidia>
References: <cover.1716883239.git.nicolinc@nvidia.com>
 <e7dab374702aaac8dc81b95ddf89c94befe409dd.1716883239.git.nicolinc@nvidia.com>
 <20240612122925.GA19897@nvidia.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20240612122925.GA19897@nvidia.com>
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 18:50:26.1274
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 943b6236-81a6-49bd-cc62-08dc8b1085ee
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource:
	DS1PEPF00017097.namprd05.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6376

On Wed, Jun 12, 2024 at 09:29:25AM -0300, Jason Gunthorpe wrote:
> On Tue, May 28, 2024 at 01:09:53AM -0700, Nicolin Chen wrote:
> 
> > +/* MMIO helpers */
> > +#define REG_CMDQV(_cmdqv, _regname) \
> > +	((_cmdqv)->base + TEGRA241_CMDQV_##_regname)
> > +#define REG_VINTF(_vintf, _regname) \
> > +	((_vintf)->base + TEGRA241_VINTF_##_regname)
> > +#define REG_VCMDQ_PAGE0(_vcmdq, _regname) \
> > +	((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname)
> > +#define REG_VCMDQ_PAGE1(_vcmdq, _regname) \
> > +	((_vcmdq)->page1 + TEGRA241_VCMDQ_##_regname)
> 
> This looks OK now
> 
> I didn't see any thing else really important in this patch
> 
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> 
> > +static inline int cmdqv_write_config(struct tegra241_cmdqv *cmdqv, u32 regval)
> > +{
> > +	return tegra241_cmdqv_write_config(cmdqv,
> > +					   cmdqv->base + TEGRA241_CMDQV_CONFIG,
> > +					   cmdqv->base + TEGRA241_CMDQV_STATUS,
> > +					   regval, "CMDQV: ", NULL);
> 
> However it would be good to go and fix these case to use the REG_xx
> macros, I noticed several.

Will respin a v9. Thanks!

Nicolin