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Wed, 12 Jun 2024 14:45:43 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Date: Wed, 12 Jun 2024 14:45:31 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AEB:EE_|MW4PR12MB7215:EE_ X-MS-Office365-Filtering-Correlation-Id: 25e9788e-575d-4828-06d6-08dc8b290a7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230034|36860700007|376008|1800799018|82310400020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fV1M2gXZ5jpmDUn+JOkVD5JoHFIzjBIP+Tz4TIgZopJQ06bj4IQIAk85BSyE?= =?us-ascii?Q?EIqvd+55a2CUPe2iS0r8QdQKLu7VLywtP1+OuCwtkI0hpZEEcBBvVv4U6t65?= =?us-ascii?Q?T7L3as53xmoxiPDuInQt/V3ygiIqJDm0ZRMFH7Ps3wdetVkdn+BnQ+Zd8NrY?= =?us-ascii?Q?9Ulkk7YKYTmfSZtLNlS502WPYPvVTIJTsq/DUgGiuk1RHKvnZxYWMLdZG2xv?= =?us-ascii?Q?F5qWsb2Ba6neS56rx5o80UpmVzFuEJapMYFNvkN+rjrCb+DoO9Igz0P5G7us?= =?us-ascii?Q?v5FfKYW8NwaZNs9DSJvfbAsvvJRc48hnYmWOw/JkXSnez19YpyrK1k51L641?= =?us-ascii?Q?WK2Y2teFtm+sLoD6tpQGQxtshs5hFDQOr/uBs0qBqDw13g1NxY9w1HnHBSHs?= =?us-ascii?Q?lnqDMwN0TMpNq8SAu1H42hwWr9AA2aP/8lM9In+M4MCb5mg5gJF3JaXEJfk0?= =?us-ascii?Q?nNr7RoKZYEPvLee4hKuHqoucHKk2Nrs/28U+JC1njBWZ0XiThE0EiAuUY3CJ?= =?us-ascii?Q?24lph6dP/TXi6Dg314rv4uVf9iPgiYCQ+bl27CXqheGklV7lgNyeSyA2vvZE?= =?us-ascii?Q?zIVNwgVvmQk1KvsTmb/sMO8qI2cDgQHJoZ4sTjdwmQwHP6WvXcB6sDwWv5cC?= =?us-ascii?Q?HDsQFKZb6ySQzGCEcw/hpqZrU6Fao6LMUylVhQ+vwb4mrTZ5q6mEeHP/RJvy?= =?us-ascii?Q?4D0WkWrOMisiNGU4J1TG2syU5vl261+U3lobfeRKNGJn4H1an78h9o7yJhch?= =?us-ascii?Q?hZcHQ3xFEoXvPbIzcbZTP/xmVWXSR/S9LSeNKR3jDz8ojIE1jYJW3RRil7YG?= =?us-ascii?Q?n2LzDLP2KXAdY6db8/yk+EajZqPLdvDRF4sukZsvCZjZDugiOlfaCMoq9e6u?= =?us-ascii?Q?k7Eo48lxF70sX6u+99NwLxHrqN/4PC7sW/YcpO8nvwueLyEO+V34W+3CV+Vh?= =?us-ascii?Q?MN4EDYXfgupPEDhExISm8oKubadSFn0TBCQewjatijN+HJCbChPlPOwiux4A?= =?us-ascii?Q?KZxUOrtdcmEzS63946K3DfDo3OCA2OceA5anwwfQhA/fjquwEJ/Hmok7W32N?= =?us-ascii?Q?e05gBzQ8+KtHBMoTltZ6ay0BKZja64tZZcijsPLIPH3w9aB3akKvoTw8yYAh?= =?us-ascii?Q?FD4zTbUWdvR1Y2lFjytzpujMgh+R9681CQ5qULeo/dGDPMewfo1lT3zVnQ90?= =?us-ascii?Q?tl8naU09RNNA23UlJ8cU0m9/sQEdC/8X2kWdlTImJvtNoyn0ye2KxLRaYPQh?= =?us-ascii?Q?wKZfOKYk23WgoC3VVD7SDXrRT9yPo6WXFzHhaYEJPU3L6y/Polr5+5CAffQV?= =?us-ascii?Q?Y/QrKdAD3MLKNuNsnGZ6VFL9mpR8wZLL23ChHP2E2DT1lee+d0iHtuupi/G3?= =?us-ascii?Q?xbR3Vp9+hVQcp4snSDAdPBoHwbJFFSHtTH3nqTbPYxLdi42mGQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230034)(36860700007)(376008)(1800799018)(82310400020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2024 21:45:56.4847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25e9788e-575d-4828-06d6-08dc8b290a7f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7215 The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a quirk flag to accommodate that. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c864c634cd23..ba0e24d5ffbf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -345,6 +345,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + return; + } + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); return; @@ -690,7 +695,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 180c0b1e0658..01227c0de290 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -543,6 +543,9 @@ struct arm_smmu_queue { u32 __iomem *prod_reg; u32 __iomem *cons_reg; + +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ + u32 quirks; }; struct arm_smmu_queue_poll { -- 2.43.0