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([2a00:f41:900a:a4b1:9ab2:4d92:821a:bb76]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ec06519289sm2881781fa.2.2024.06.13.09.46.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Jun 2024 09:46:25 -0700 (PDT) Message-ID: <37bbd466-742a-4a23-b3f7-97f8da109608@linaro.org> Date: Thu, 13 Jun 2024 18:46:22 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/8] clk: qcom: Add support for Display clock Controllers on SA8775P To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_jkona@quicinc.com, quic_imrashai@quicinc.com References: <20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com> <20240612-sa8775p-mm-clock-controllers-v1-6-db295a846ee7@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240612-sa8775p-mm-clock-controllers-v1-6-db295a846ee7@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/12/24 12:47, Taniya Das wrote: > Add support for display0 and display1 clock controllers on SA8775P > platform. > > Signed-off-by: Taniya Das > --- Please merge this into one to save on boilerplate, take a look at dispcc-sc8280xp.c Konrad