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Message-ID: <f2d81804-f4a3-d813-cbb0-5c4ada6a3fda@quicinc.com>
Date: Thu, 13 Jun 2024 22:21:58 +0530
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Subject: Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs
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To: Shivnandan Kumar <quic_kshivnan@quicinc.com>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <djakov@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <srinivas.kandagatla@linaro.org>
CC: <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-pm@vger.kernel.org>,
        <quic_rgottimu@quicinc.com>, <conor+dt@kernel.org>,
        <dmitry.baryshkov@linaro.org>, <abel.vesa@linaro.org>
References: <20240604011157.2358019-1-quic_sibis@quicinc.com>
 <20240604011157.2358019-4-quic_sibis@quicinc.com>
 <b9ee77da-bd51-4d32-8f35-d38fe8b77f44@quicinc.com>
From: Sibi Sankar <quic_sibis@quicinc.com>
In-Reply-To: <b9ee77da-bd51-4d32-8f35-d38fe8b77f44@quicinc.com>
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On 6/6/24 14:39, Shivnandan Kumar wrote:
> 
> 
> On 6/4/2024 6:41 AM, Sibi Sankar wrote:
>> Add the CPU and LLCC BWMONs on X1E80100 SoCs.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>

Hey Shiv,
Thanks for taking time to review the series :)

>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
>>   1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 1929c34ae70a..d86c4d3be126 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
>>               };
>>           };
>> +        pmu@24091000 {
>> +            compatible = "qcom,x1e80100-llcc-bwmon", 
>> "qcom,sc7280-llcc-bwmon";
>> +            reg = <0 0x24091000 0 0x1000>;
>> +
>> +            interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +            interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt 
>> SLAVE_EBI1 3>;
>> +
>> +            operating-points-v2 = <&llcc_bwmon_opp_table>;
>> +
>> +            llcc_bwmon_opp_table: opp-table {
>> +                compatible = "operating-points-v2";
>> +
>> +                opp-0 {
> 
> Nitpick,In one table, we start from ‘opp-0,’ while in the other table, 
> it begins with ‘opp-1,it is better to make it consistent across table.
> 

Will fix it in the next re-spin.

-Sibi

>> +                    opp-peak-kBps = <800000>;
>>               reg = <0 0x25000000 0 0x200000>,
...
[snip]
...
> 
> 
> Thanks,
> Shivnandan