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([2a00:f41:900a:a4b1:9ab2:4d92:821a:bb76]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca28259cbsm289479e87.62.2024.06.13.10.05.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Jun 2024 10:05:25 -0700 (PDT) Message-ID: <4fdb62a8-df00-4cd2-9c96-74afcae3ac5c@linaro.org> Date: Thu, 13 Jun 2024 19:05:22 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Bartosz Golaszewski , Shazad Hussain Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, quic_jkona@quicinc.com, quic_imrashai@quicinc.com References: <20240612-sa8775p-v2-gcc-gpucc-fixes-v2-0-adcc756a23df@quicinc.com> <20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/12/24 13:08, Taniya Das wrote: > Update the force mem core bit for UFS ICE clock to force the core on > signal to remain active during halt state of the clk. If force mem > core bit of the clock is not set, the memories of the subsystem will > not retain the logic across power states. > > Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") > Signed-off-by: Taniya Das > --- Reviewed-by: Konrad Dybcio Konrad