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Thu, 13 Jun 2024 17:18:49 GMT Received: from [10.131.33.37] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Jun 2024 10:18:43 -0700 Message-ID: <6b46ed87-e225-bf74-dbe1-ad8913c585c7@quicinc.com> Date: Thu, 13 Jun 2024 22:48:40 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs Content-Language: en-US To: Konrad Dybcio , , , , , CC: , , , , , , , , References: <20240604011157.2358019-1-quic_sibis@quicinc.com> <20240604011157.2358019-4-quic_sibis@quicinc.com> <4ef1d9a9-6a0e-4324-b6d5-2ae225855b03@linaro.org> From: Sibi Sankar In-Reply-To: <4ef1d9a9-6a0e-4324-b6d5-2ae225855b03@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fGiutENxV6EMnPU2IEyDGjLfvd54Edlk X-Proofpoint-ORIG-GUID: fGiutENxV6EMnPU2IEyDGjLfvd54Edlk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-13_11,2024-06-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 spamscore=0 suspectscore=0 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406130124 On 6/6/24 15:26, Konrad Dybcio wrote: > On 4.06.2024 3:11 AM, Sibi Sankar wrote: >> Add the CPU and LLCC BWMONs on X1E80100 SoCs. Hey Konrad, Thanks for taking time to review the series :) >> >> Signed-off-by: Sibi Sankar >> --- >> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++ >> 1 file changed, 169 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> index 1929c34ae70a..d86c4d3be126 100644 >> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 { >> }; >> }; >> >> + pmu@24091000 { >> + compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; >> + reg = <0 0x24091000 0 0x1000>; >> + >> + interrupts = ; >> + >> + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; > > QCOM_ICC_TAG_ACTIVE_ONLY ack > > [...] > >> + >> + cpu0_bwmon_opp_table: opp-table { >> + compatible = "operating-points-v2"; > > I *think* if you add opp-shared here, you can reference the same OPP table > from all 3 BWMONs without anything exploding. I did try this out before IIRC this resulted in just one device vote in the interconnect_summary. Didn't investigate further before because it was breaking bindings anyway. Will have another look at it. -Sibi > > Konrad