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Thu, 13 Jun 2024 15:40:37 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-515-g87b2bad5a-fm-20240604.001-g87b2bad5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: In-Reply-To: <20240613185902.GB2286020-robh@kernel.org> References: <20240612-boston-syscon-v2-0-9f8e1a07fa63@flygoat.com> <20240612-boston-syscon-v2-7-9f8e1a07fa63@flygoat.com> <20240612-unstuffed-figure-966c90af52bc@spud> <20240613185902.GB2286020-robh@kernel.org> Date: Thu, 13 Jun 2024 20:40:18 +0100 From: "Jiaxun Yang" To: "Rob Herring" Cc: "Conor Dooley" , "Lee Jones" , "Krzysztof Kozlowski" , "Conor Dooley" , "paulburton@kernel.org" , "Thomas Bogendoerfer" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "linux-mips@vger.kernel.org" Subject: Re: [PATCH v2 7/8] du-bindings: mips: cpu: Add img,mips compatible Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B46=E6=9C=8813=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=E5= =8D=887:59=EF=BC=8CRob Herring=E5=86=99=E9=81=93=EF=BC=9A > On Wed, Jun 12, 2024 at 05:59:24PM +0100, Jiaxun Yang wrote: >>=20 >>=20 >> =E5=9C=A82024=E5=B9=B46=E6=9C=8812=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B= =E5=8D=885:39=EF=BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A >> > On Wed, Jun 12, 2024 at 12:56:26PM +0100, Jiaxun Yang wrote: >> >> This compatible is used by boston.dts. >> >>=20 >> >> Signed-off-by: Jiaxun Yang >> >> --- >> >> note: This is a wildcard compatible for all MIPS CPUs, >> >> I think we should use something like "riscv" for riscv. >> > >> > riscv systems, other than simulators etc are not meant to use the >> > "riscv" compatible. All of the real CPUs use "vendor,cpu", "riscv". >> > I'd suggest you add specific compatibles for your CPUs. >>=20 >> Boston can be combined with many different CPUs, thus we need to have >> such compatibles. > > Then you'll need different DTs. Different h/w, different DT. The board have 9 CPU types in total, with hundreds of different possible CPU topologies. Maintaining separate DT for them seems impossible in ker= nel. We can potentially patch this in bootloader, but for existing firmware i= t's being doing like this for years. I can see for RISC-V QEMU generated DTB= is using a single "riscv" compatible and I do think it's a similar problem. I think it's better to document it and warn people only to use it in lim= ited circumstances, instead of keeping such usage in grey area. Thanks > > No way we're taking a generic compatible like this. > > Rob --=20 - Jiaxun