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Date: Fri, 14 Jun 2024 00:16:42 +0200
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>, 
	Robin Murphy <robin.murphy@arm.com>, Heiko Stuebner <heiko@sntech.de>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Oded Gabbay <ogabbay@kernel.org>, Tomeu Vizoso <tomeu.vizoso@tomeuvizoso.net>, 
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, 
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, 
	Thomas Zimmermann <tzimmermann@suse.de>, Philipp Zabel <p.zabel@pengutronix.de>, 
	Sumit Semwal <sumit.semwal@linaro.org>, Christian =?utf-8?B?S8O2bmln?= <christian.koenig@amd.com>, 
	iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, 
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, 
	dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org
Subject: Re: [PATCH 4/9] arm64: dts: rockchip: Add nodes for NPU and its MMU
 to rk3588s
Message-ID: <rrmiv7lwj2refsmmdijwpccniw5chnyoma2gxcueeemxypbodx@mjpdrbqs37ce>
References: <20240612-6-10-rocket-v1-0-060e48eea250@tomeuvizoso.net>
 <20240612-6-10-rocket-v1-4-060e48eea250@tomeuvizoso.net>
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Hi,

On Wed, Jun 12, 2024 at 03:52:57PM GMT, Tomeu Vizoso wrote:
> See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
>=20
> This is a derivative of NVIDIA's NVDLA, but with its own front-end
> processor.
>=20
> Mostly taken from downstream.
>=20
> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
> ---

Looking at the TRM I noticed, that this register is not mapped:

RKNN_global_operation_enable
Address: Operational Base + offset (0xF008)

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 53 +++++++++++++++++++++++++=
++++++
>  1 file changed, 53 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/=
dts/rockchip/rk3588s.dtsi
> index 6ac5ac8b48ab..a5d53578c8f6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -2665,6 +2665,59 @@ gpio4: gpio@fec50000 {
>  			#interrupt-cells =3D <2>;
>  		};
>  	};
> +
> +	rknn: npu@fdab0000 {
> +		compatible =3D "rockchip,rk3588-rknn", "rockchip,rknn";
> +		reg =3D <0x0 0xfdab0000 0x0 0x9000>,
> +		      <0x0 0xfdac0000 0x0 0x9000>,
> +		      <0x0 0xfdad0000 0x0 0x9000>;
> +		interrupts =3D <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names =3D "npu0_irq", "npu1_irq", "npu2_irq";
> +		clocks =3D <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
> +			 <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
> +			 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
> +			 <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
> +		clock-names =3D "clk_npu",
> +			      "aclk0", "aclk1", "aclk2",
> +			      "hclk0", "hclk1", "hclk2",
> +			      "pclk";
> +		assigned-clocks =3D <&scmi_clk SCMI_CLK_NPU>;
> +		assigned-clock-rates =3D <200000000>;
> +		resets =3D <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN=
2>,
> +			 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
> +		reset-names =3D "srst_a0", "srst_a1", "srst_a2",
> +			      "srst_h0", "srst_h1", "srst_h2";
> +		power-domains =3D <&power RK3588_PD_NPUTOP>,
> +				<&power RK3588_PD_NPU1>,
> +				<&power RK3588_PD_NPU2>;
> +		power-domain-names =3D "npu0", "npu1", "npu2";
> +		iommus =3D <&rknn_mmu>;
> +		status =3D "disabled";
> +	};
> +
> +	rknn_mmu: iommu@fdab9000 {
> +		compatible =3D "rockchip,rk3588-iommu";
> +		reg =3D <0x0 0xfdab9000 0x0 0x100>,
> +		      <0x0 0xfdaba000 0x0 0x100>,
> +		      <0x0 0xfdaca000 0x0 0x100>,
> +		      <0x0 0xfdada000 0x0 0x100>;
> +		interrupts =3D <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names =3D "npu0_mmu", "npu1_mmu", "npu2_mmu";
> +		clocks =3D <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
> +			 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
> +		clock-names =3D "aclk0", "aclk1", "aclk2",
> +			      "iface0", "iface1", "iface2";
> +		#iommu-cells =3D <0>;
> +		power-domains =3D <&power RK3588_PD_NPUTOP>,
> +				<&power RK3588_PD_NPU1>,
> +				<&power RK3588_PD_NPU2>;
> +		power-domain-names =3D "npu0", "npu1", "npu2";
> +		status =3D "disabled";
> +	};
>  };
> =20
>  #include "rk3588s-pinctrl.dtsi"
>=20
> --=20
> 2.45.2
>=20
>=20

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