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Date: Fri, 14 Jun 2024 09:06:20 +0100
From: Conor Dooley <conor.dooley@microchip.com>
To: Jesse Taube <jesse@rivosinc.com>
CC: <linux-riscv@lists.infradead.org>, Jonathan Corbet <corbet@lwn.net>, Paul
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Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Add Zicclsm ISA extension
 description.
Message-ID: <20240614-broaden-bluish-8b2fe892db55@wendy>
References: <20240613191616.2101821-1-jesse@rivosinc.com>
 <20240613191616.2101821-3-jesse@rivosinc.com>
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On Thu, Jun 13, 2024 at 03:16:11PM -0400, Jesse Taube wrote:
> Add description for Zicclsm ISA extension.
>=20
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> V1 -> V2:
>  - New patch
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Do=
cumentation/devicetree/bindings/riscv/extensions.yaml
> index cfed80ad5540..9f6aae1f5b65 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -317,6 +317,13 @@ properties:
>              The standard Zicboz extension for cache-block zeroing as rat=
ified
>              in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> =20
> +        - const: zicclsm
> +          description:
> +            The standard Zicclsm extension for misaligned support for al=
l regular
> +            load and store instructions (including scalar and vector) bu=
t not AMOs
> +            or other specialized forms of memory access. Defined in the
> +            RISC-V RVA Profiles Specification.

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> +
>          - const: zicntr
>            description:
>              The standard Zicntr extension for base counters and timers, =
as
> --=20
> 2.43.0
>=20

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