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Message-ID: <fbf2be8d31579d1c9305fd961751fc6f0a4b4556.camel@redhat.com>
Subject: Re: [PATCH next-next] net: phy: realtek: add support for rtl8224
 2.5Gbps PHY
From: Paolo Abeni <pabeni@redhat.com>
To: Marek =?ISO-8859-1?Q?Beh=FAn?= <kabel@kernel.org>, Chris Packham
	 <Chris.Packham@alliedtelesis.co.nz>
Cc: "andrew@lunn.ch" <andrew@lunn.ch>, "hkallweit1@gmail.com"
 <hkallweit1@gmail.com>, "linux@armlinux.org.uk" <linux@armlinux.org.uk>, 
 "davem@davemloft.net" <davem@davemloft.net>, "edumazet@google.com"
 <edumazet@google.com>,  "kuba@kernel.org" <kuba@kernel.org>,
 "netdev@vger.kernel.org" <netdev@vger.kernel.org>, 
 "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
 "ericwouds@gmail.com" <ericwouds@gmail.com>
Date: Fri, 14 Jun 2024 10:18:47 +0200
In-Reply-To: <20240612090707.7da3fc01@dellmb>
References: <20240611053415.2111723-1-chris.packham@alliedtelesis.co.nz>
	 <c3d699a1-2f24-41c5-b0a7-65db025eedbc@alliedtelesis.co.nz>
	 <20240612090707.7da3fc01@dellmb>
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On Wed, 2024-06-12 at 09:07 +0200, Marek Beh=C3=BAn wrote:
> On Tue, 11 Jun 2024 20:42:43 +0000
> Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
>=20
> > +cc Eric W and Marek.
> >=20
> > On 11/06/24 17:34, Chris Packham wrote:
> > > The Realtek RTL8224 PHY is a 2.5Gbps capable PHY. It only uses the
> > > clause 45 MDIO interface and can leverage the support that has alread=
y
> > > been added for the other 822x PHYs.
> > >=20
> > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > > ---
> > >=20
> > > Notes:
> > >      I'm currently testing this on an older kernel because the board =
I'm
> > >      using has a SOC/DSA switch that has a driver in openwrt for Linu=
x 5.15.
> > >      I have tried to selectively back port the bits I need from the o=
ther
> > >      rtl822x work so this should be all that is required for the rtl8=
224.
> > >     =20
> > >      There's quite a lot that would need forward porting get a workin=
g system
> > >      against a current kernel so hopefully this is small enough that =
it can
> > >      land while I'm trying to figure out how to untangle all the othe=
r bits.
> > >     =20
> > >      One thing that may appear lacking is the lack of rate_matching s=
upport.
> > >      According to the documentation I have know the interface used on=
 the
> > >      RTL8224 is (q)uxsgmii so no rate matching is required. As I'm st=
ill
> > >      trying to get things completely working that may change if I get=
 new
> > >      information.
> > >=20
> > >   drivers/net/phy/realtek.c | 8 ++++++++
> > >   1 file changed, 8 insertions(+)
> > >=20
> > > diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
> > > index 7ab41f95dae5..2174893c974f 100644
> > > --- a/drivers/net/phy/realtek.c
> > > +++ b/drivers/net/phy/realtek.c
> > > @@ -1317,6 +1317,14 @@ static struct phy_driver realtek_drvs[] =3D {
> > >   		.resume         =3D rtlgen_resume,
> > >   		.read_page      =3D rtl821x_read_page,
> > >   		.write_page     =3D rtl821x_write_page,
> > > +	}, {
> > > +		PHY_ID_MATCH_EXACT(0x001ccad0),
> > > +		.name		=3D "RTL8224 2.5Gbps PHY",
> > > +		.get_features   =3D rtl822x_c45_get_features,
> > > +		.config_aneg    =3D rtl822x_c45_config_aneg,
> > > +		.read_status    =3D rtl822x_c45_read_status,
> > > +		.suspend        =3D genphy_c45_pma_suspend,
> > > +		.resume         =3D rtlgen_c45_resume,
> > >   	}, {
> > >   		PHY_ID_MATCH_EXACT(0x001cc961),
> > >   		.name		=3D "RTL8366RB Gigabit Ethernet" =20
>=20
> Don't you need rtl822xb_config_init for serdes configuration?

Marek, I read the above as you would prefer to have such support
included from the beginning, as such I'm looking forward a new version
of this patch.

Please raise a hand if I read too much in your reply.

Thanks!

Paolo