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Fri, 14 Jun 2024 01:23:10 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Fri, 14 Jun 2024 01:23:05 -0700 Date: Fri, 14 Jun 2024 09:22:47 +0100 From: Conor Dooley To: Jesse Taube CC: , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Evan Green , Andrew Jones , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , , , Subject: Re: [PATCH v2 3/6] RISC-V: Check scalar unaligned access on all CPUs Message-ID: <20240614-padded-mammal-d956735c1293@wendy> References: <20240613191616.2101821-1-jesse@rivosinc.com> <20240613191616.2101821-4-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="5roV/dfZvNvEhY/C" Content-Disposition: inline In-Reply-To: <20240613191616.2101821-4-jesse@rivosinc.com> --5roV/dfZvNvEhY/C Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jun 13, 2024 at 03:16:12PM -0400, Jesse Taube wrote: > Originally, the check_unaligned_access_emulated_all_cpus function > only checked the boot hart. This fixes the function to check all > harts. This seems like it should be split out and get a Fixes: tag & a cc: stable. > Check for Zicclsm before checking for unaligned access. This will > greatly reduce the boot up time as finding the access speed is no longer > necessary. >=20 > Signed-off-by: Jesse Taube > --- > V1 -> V2: > - New patch > --- > arch/riscv/kernel/traps_misaligned.c | 23 ++++++---------------- > arch/riscv/kernel/unaligned_access_speed.c | 23 +++++++++++++--------- > 2 files changed, 20 insertions(+), 26 deletions(-) >=20 > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index b62d5a2f4541..8fadbe00dd62 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -526,31 +526,17 @@ int handle_misaligned_store(struct pt_regs *regs) > return 0; > } > =20 > -static bool check_unaligned_access_emulated(int cpu) > +static void check_unaligned_access_emulated(struct work_struct *unused) > { > + int cpu =3D smp_processor_id(); > long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); > unsigned long tmp_var, tmp_val; > - bool misaligned_emu_detected; > =20 > *mas_ptr =3D RISCV_HWPROBE_MISALIGNED_UNKNOWN; > =20 > __asm__ __volatile__ ( > " "REG_L" %[tmp], 1(%[ptr])\n" > : [tmp] "=3Dr" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); > - > - misaligned_emu_detected =3D (*mas_ptr =3D=3D RISCV_HWPROBE_MISALIGNED_E= MULATED); > - /* > - * If unaligned_ctl is already set, this means that we detected that all > - * CPUS uses emulated misaligned access at boot time. If that changed > - * when hotplugging the new cpu, this is something we don't handle. > - */ > - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) { > - pr_crit("CPU misaligned accesses non homogeneous (expected all emulate= d)\n"); > - while (true) > - cpu_relax(); > - } > - > - return misaligned_emu_detected; > } > =20 > bool check_unaligned_access_emulated_all_cpus(void) > @@ -562,8 +548,11 @@ bool check_unaligned_access_emulated_all_cpus(void) > * accesses emulated since tasks requesting such control can run on any > * CPU. > */ > + schedule_on_each_cpu(check_unaligned_access_emulated); > + > for_each_online_cpu(cpu) > - if (!check_unaligned_access_emulated(cpu)) > + if (per_cpu(misaligned_access_speed, cpu) > + !=3D RISCV_HWPROBE_MISALIGNED_EMULATED) > return false; > =20 > unaligned_ctl =3D true; > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kern= el/unaligned_access_speed.c > index a9a6bcb02acf..70c1588fc353 100644 > --- a/arch/riscv/kernel/unaligned_access_speed.c > +++ b/arch/riscv/kernel/unaligned_access_speed.c > @@ -259,23 +259,28 @@ static int check_unaligned_access_speed_all_cpus(vo= id) > kfree(bufs); > return 0; > } > +#endif /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ > =20 > static int check_unaligned_access_all_cpus(void) > { > - bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); > + bool all_cpus_emulated; > + int cpu; > =20 > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) { > + for_each_online_cpu(cpu) { > + per_cpu(misaligned_access_speed, cpu) =3D RISCV_HWPROBE_MISALIGNED_FA= ST; > + } > + return 0; > + } > + > + all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); > + > +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS Can we make this an IS_ENABLED() please? Thanks, Conor. > if (!all_cpus_emulated) > return check_unaligned_access_speed_all_cpus(); > +#endif > =20 > return 0; > } > -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ > -static int check_unaligned_access_all_cpus(void) > -{ > - check_unaligned_access_emulated_all_cpus(); > - > - return 0; > -} > -#endif > =20 > arch_initcall(check_unaligned_access_all_cpus); > --=20 > 2.43.0 >=20 --5roV/dfZvNvEhY/C Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZmv91wAKCRB4tDGHoIJi 0reHAQDJzCDTih2CT5+8AGBLj1gklSGmS/R+h5QMKj0uL8S0zQEAqTT7zZH5px5I 8XwHyIp3NfUTa9Qm5JgQqXy58YGrLgQ= =jw9t -----END PGP SIGNATURE----- --5roV/dfZvNvEhY/C--