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Fri, 14 Jun 2024 01:37:19 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Fri, 14 Jun 2024 01:37:13 -0700 Date: Fri, 14 Jun 2024 09:36:55 +0100 From: Conor Dooley To: Jesse Taube CC: , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Evan Green , Andrew Jones , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , , , Subject: Re: [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses supported. Message-ID: <20240614-viral-dinghy-71d5f6585a55@wendy> References: <20240613191616.2101821-1-jesse@rivosinc.com> <20240613191616.2101821-5-jesse@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Ytzm/oHaDkbsSGqU" Content-Disposition: inline In-Reply-To: <20240613191616.2101821-5-jesse@rivosinc.com> --Ytzm/oHaDkbsSGqU Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jun 13, 2024 at 03:16:13PM -0400, Jesse Taube wrote: > --- a/arch/riscv/kernel/unaligned_access_speed.c > +++ b/arch/riscv/kernel/unaligned_access_speed.c > @@ -19,7 +19,8 @@ > #define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE) > #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80) > =20 > -DEFINE_PER_CPU(long, misaligned_access_speed); > +DEFINE_PER_CPU(long, misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGN= ED_UNKNOWN; > +DEFINE_PER_CPU(long, vector_misaligned_access) =3D RISCV_HWPROBE_VEC_MIS= ALIGNED_UNSUPPORTED; > =20 > #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS > static cpumask_t fast_misaligned_access; > @@ -268,12 +269,18 @@ static int check_unaligned_access_all_cpus(void) > =20 > if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) { > for_each_online_cpu(cpu) { > +#ifdef CONFIG_RISCV_VECTOR_MISALIGNED > + per_cpu(vector_misaligned_access, cpu) =3D RISCV_HWPROBE_VEC_MISALIGN= ED_FAST; > +#endif > +#ifdef CONFIG_RISCV_MISALIGNED > per_cpu(misaligned_access_speed, cpu) =3D RISCV_HWPROBE_MISALIGNED_FA= ST; > +#endif Can you IS_ENABLED()-ify these two as well please? --Ytzm/oHaDkbsSGqU Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZmwBJwAKCRB4tDGHoIJi 0o83AP4l3yMCtJznhon+dFQUAVsO6wRiQb2NfRzHzaOsUmMyyQEA3rLtvEQrCOU7 yZz/D4drHvHR3eCHR57Lvgb+yeiQJww= =ToT+ -----END PGP SIGNATURE----- --Ytzm/oHaDkbsSGqU--