Received: by 2002:a89:413:0:b0:1fd:dba5:e537 with SMTP id m19csp695864lqs; Fri, 14 Jun 2024 03:02:16 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCW6GRjy/sf7xGghqXIVbjmBzDdImJUkD9wtb0JN70Lt54T1z4Qegt3Sqx7tJX14cKd1FGNQ0uZv0ZTPlpT+k+MWB6vzSmd5W+y4j5/NzA== X-Google-Smtp-Source: AGHT+IE2VBpigExCUtK28MeOtWEAgu5+ZsMAl+WxPEPEfdJg9nA6lF4a+FaIbEup8Mml1aSQEnBN X-Received: by 2002:a17:907:b9d6:b0:a68:fb0c:b294 with SMTP id a640c23a62f3a-a6f60de3434mr127240766b.77.1718359336166; Fri, 14 Jun 2024 03:02:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1718359336; cv=pass; d=google.com; s=arc-20160816; b=D8IfVMQqwzPTRNJVH/RqLAkD3dUNyERAtkOvGBRH3PVqic89roiX/VOV7nETd6GLMN AuGbMF2GINugkezju/6+ctgSiTAnajDtwTW7pF8q8bJq9A6fUsT34C/V4FikWq4pG73J MzQAjUWG6AiDcFsteTrtexka6tUUZyDMBci7sYHeyYhEUvFxgjRMu3+Ddx0H9bXREitU aymZ+/L3i2EZvG7IDPSITYNtZhN6dkmiLntYrF4pBZoNl8tz0l/Q2vuANWsjvDGoAfWM 3D3tp2EKrvFPDCvB8W5AyF7eUAbJg75t9ls7bYQGEnEk6zeL/yXdoC9MSqc85xo3JiuP eT9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=BUbA/JO27H+YWfW1ZtfdHi/F242NE6HU9B3HuEjAETY=; fh=Hu+aAStr1vvh4d0qPv6RByCsl0cCVQ9cHKHEOIZh1I8=; b=UZq6wku4KngXZAg+dmHQap2HzJQnZS0twhMtb1H24qfaQpV3cinXSe2kxRUzvM+Agz KeKVR9qhnGR6TEEIOhAFU3p9wgvJAlAbpcUSN4vORUkOeZpdLYcF/VMoZlsimzeVjTq0 iGaQ6S6q8xqa8cFi4C240aKoDgClIU+MgsGfK5eEDRHtekcwKdVR+AWoW+gN3XSbtR3i sluw5VRYocfc/lQ1KZ0KdbWXaxiFIA1lm0a/GO692frEIbLOwIx250BAOrR7PV67uw9D y7L03R3DSJRHnkxfhf2m3LgPRxnYpxyuqYc/Ns5SqKe0tSjC3hb+ThQvxJUIjHiv/+A0 qUCA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mJWt5qNv; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-214712-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-214712-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id a640c23a62f3a-a6f56dd6da4si164709566b.456.2024.06.14.03.02.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 03:02:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-214712-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mJWt5qNv; arc=pass (i=1 dkim=pass dkdomain=intel.com dmarc=pass fromdomain=linux.intel.com); spf=pass (google.com: domain of linux-kernel+bounces-214712-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-214712-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id B34BE1F28493 for ; Fri, 14 Jun 2024 10:02:15 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 30B6C199E86; Fri, 14 Jun 2024 09:59:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mJWt5qNv" Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD171195FE6; Fri, 14 Jun 2024 09:59:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718359165; cv=none; b=dSBvytEVYIuAhakS1F0YY10mKVPgSTL+4w9YpOHG7GfhVHjddU27r8o/3P8dlAg1WWzxsSUZf2ltyhMr7cKSCWmmeAww8XkbTxkv8GA2QVceVm5x6a9V0BINFHPt8Ea8lhN5/n+7lZLC0NY6NufWBNt4npclICxMwDzjRrq2Jp8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718359165; c=relaxed/simple; bh=ECdX67CT706dj0mlzCOMRqGiltd61ccVv16An5RaII4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P3uAmv2jyzeTcQ63azGjMXGSd7BFm5+bZV60jgpgLb/BaM+XPZGpiJ8V6w6VNgZdMDyvpMQg+N9gdPVcr/AjkJco7qXUVwCjK5wQZZYzqCl+sLj8g5lPqmxYlEkwybIlxGOUKKWptKROYg/pmQmOwHtDx4w3KvOEDw8XEfIbN9k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mJWt5qNv; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718359164; x=1749895164; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ECdX67CT706dj0mlzCOMRqGiltd61ccVv16An5RaII4=; b=mJWt5qNvl7FDVUzcbeMrwWeHIhZaZIr/4CEY05VtCy84AqHANY9oSyMT 5bayERdHCqYb0mZ2zmXbjHvvFDGUKPV0II3A+n4X8TVQty5OFfPccRBCw JNLsFdp32TVa6iaCU+xGyynOQgvTgC7JGYWphbVzo90V8U7vV1jFVuOhy u7LpA45oNte3ZyKyGgneP21TAiOnGQFCcDO5QUN10qu+7CgHw8Jw2jPU2 lceZ/tp00mAsQyn174c9Auj8PtP+oQI1Qt5nZHX3xN0Sr/le+RnTe7R2f /H3VByVbrk8nQ5Rw93y1Tl2MEIZZ/Ma7kF/8ETgXLCuglif+R38RGRNd+ g==; X-CSE-ConnectionGUID: LClRbMp0SjOUkK2HOd9qiQ== X-CSE-MsgGUID: CiVTX/oVSZKyUyTHwnxCDg== X-IronPort-AV: E=McAfee;i="6700,10204,11102"; a="15466687" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="15466687" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 02:59:23 -0700 X-CSE-ConnectionGUID: puMiRCSZT32mQjsnE6YUJQ== X-CSE-MsgGUID: DQWwLt08TtyIctJ4+UFzKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="77930011" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa001.jf.intel.com with ESMTP; 14 Jun 2024 02:59:17 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id D1FFA29E6; Fri, 14 Jun 2024 12:59:08 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Ard Biesheuvel , Baoquan He , "H. Peter Anvin" , "Kirill A. Shutemov" , "K. Y. Srinivasan" , Haiyang Zhang , kexec@lists.infradead.org, linux-hyperv@vger.kernel.org, linux-acpi@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Dave Hansen , Tao Liu , Michael Kelley Subject: [PATCHv12 07/19] x86/mm: Make x86_platform.guest.enc_status_change_*() return errno Date: Fri, 14 Jun 2024 12:58:52 +0300 Message-ID: <20240614095904.1345461-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240614095904.1345461-1-kirill.shutemov@linux.intel.com> References: <20240614095904.1345461-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit TDX is going to have more than one reason to fail enc_status_change_prepare(). Change the callback to return errno instead of assuming -EIO; enc_status_change_finish() changed too to keep the interface symmetric. Signed-off-by: Kirill A. Shutemov Reviewed-by: Dave Hansen Reviewed-by: Kai Huang Tested-by: Tao Liu Reviewed-by: Michael Kelley --- arch/x86/coco/tdx/tdx.c | 20 +++++++++++--------- arch/x86/hyperv/ivm.c | 22 ++++++++++------------ arch/x86/include/asm/x86_init.h | 4 ++-- arch/x86/kernel/x86_init.c | 4 ++-- arch/x86/mm/mem_encrypt_amd.c | 8 ++++---- arch/x86/mm/pat/set_memory.c | 12 +++++++----- 6 files changed, 36 insertions(+), 34 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index c1cb90369915..26fa47db5782 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -798,28 +798,30 @@ static bool tdx_enc_status_changed(unsigned long vaddr, int numpages, bool enc) return true; } -static bool tdx_enc_status_change_prepare(unsigned long vaddr, int numpages, - bool enc) +static int tdx_enc_status_change_prepare(unsigned long vaddr, int numpages, + bool enc) { /* * Only handle shared->private conversion here. * See the comment in tdx_early_init(). */ - if (enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } -static bool tdx_enc_status_change_finish(unsigned long vaddr, int numpages, +static int tdx_enc_status_change_finish(unsigned long vaddr, int numpages, bool enc) { /* * Only handle private->shared conversion here. * See the comment in tdx_early_init(). */ - if (!enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } void __init tdx_early_init(void) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 768d73de0d09..b4a851d27c7c 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -523,9 +523,9 @@ static int hv_mark_gpa_visibility(u16 count, const u64 pfn[], * transition is complete, hv_vtom_set_host_visibility() marks the pages * as "present" again. */ -static bool hv_vtom_clear_present(unsigned long kbuffer, int pagecount, bool enc) +static int hv_vtom_clear_present(unsigned long kbuffer, int pagecount, bool enc) { - return !set_memory_np(kbuffer, pagecount); + return set_memory_np(kbuffer, pagecount); } /* @@ -536,20 +536,19 @@ static bool hv_vtom_clear_present(unsigned long kbuffer, int pagecount, bool enc * with host. This function works as wrap of hv_mark_gpa_visibility() * with memory base and size. */ -static bool hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecount, bool enc) +static int hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecount, bool enc) { enum hv_mem_host_visibility visibility = enc ? VMBUS_PAGE_NOT_VISIBLE : VMBUS_PAGE_VISIBLE_READ_WRITE; u64 *pfn_array; phys_addr_t paddr; + int i, pfn, err; void *vaddr; int ret = 0; - bool result = true; - int i, pfn; pfn_array = kmalloc(HV_HYP_PAGE_SIZE, GFP_KERNEL); if (!pfn_array) { - result = false; + ret = -ENOMEM; goto err_set_memory_p; } @@ -568,10 +567,8 @@ static bool hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecount, bo if (pfn == HV_MAX_MODIFY_GPA_REP_COUNT || i == pagecount - 1) { ret = hv_mark_gpa_visibility(pfn, pfn_array, visibility); - if (ret) { - result = false; + if (ret) goto err_free_pfn_array; - } pfn = 0; } } @@ -586,10 +583,11 @@ static bool hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecount, bo * order to avoid leaving the memory range in a "broken" state. Setting * the PRESENT bits shouldn't fail, but return an error if it does. */ - if (set_memory_p(kbuffer, pagecount)) - result = false; + err = set_memory_p(kbuffer, pagecount); + if (err && !ret) + ret = err; - return result; + return ret; } static bool hv_vtom_tlb_flush_required(bool private) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index 6149eabe200f..28ac3cb9b987 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -151,8 +151,8 @@ struct x86_init_acpi { * @enc_cache_flush_required Returns true if a cache flush is needed before changing page encryption status */ struct x86_guest { - bool (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool enc); - bool (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc); + int (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool enc); + int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc); bool (*enc_tlb_flush_required)(bool enc); bool (*enc_cache_flush_required)(void); }; diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index d5dc5a92635a..a7143bb7dd93 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -134,8 +134,8 @@ struct x86_cpuinit_ops x86_cpuinit = { static void default_nmi_init(void) { }; -static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { return true; } -static bool enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return true; } +static int enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { return 0; } +static int enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return 0; } static bool enc_tlb_flush_required_noop(bool enc) { return false; } static bool enc_cache_flush_required_noop(void) { return false; } static bool is_private_mmio_noop(u64 addr) {return false; } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 422602f6039b..e7b67519ddb5 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -283,7 +283,7 @@ static void enc_dec_hypercall(unsigned long vaddr, unsigned long size, bool enc) #endif } -static bool amd_enc_status_change_prepare(unsigned long vaddr, int npages, bool enc) +static int amd_enc_status_change_prepare(unsigned long vaddr, int npages, bool enc) { /* * To maintain the security guarantees of SEV-SNP guests, make sure @@ -292,11 +292,11 @@ static bool amd_enc_status_change_prepare(unsigned long vaddr, int npages, bool if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && !enc) snp_set_memory_shared(vaddr, npages); - return true; + return 0; } /* Return true unconditionally: return value doesn't matter for the SEV side */ -static bool amd_enc_status_change_finish(unsigned long vaddr, int npages, bool enc) +static int amd_enc_status_change_finish(unsigned long vaddr, int npages, bool enc) { /* * After memory is mapped encrypted in the page table, validate it @@ -308,7 +308,7 @@ static bool amd_enc_status_change_finish(unsigned long vaddr, int npages, bool e if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) enc_dec_hypercall(vaddr, npages << PAGE_SHIFT, enc); - return true; + return 0; } static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc) diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 19fdfbb171ed..498812f067cd 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2196,7 +2196,8 @@ static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc) cpa_flush(&cpa, x86_platform.guest.enc_cache_flush_required()); /* Notify hypervisor that we are about to set/clr encryption attribute. */ - if (!x86_platform.guest.enc_status_change_prepare(addr, numpages, enc)) + ret = x86_platform.guest.enc_status_change_prepare(addr, numpages, enc); + if (ret) goto vmm_fail; ret = __change_page_attr_set_clr(&cpa, 1); @@ -2214,16 +2215,17 @@ static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc) return ret; /* Notify hypervisor that we have successfully set/clr encryption attribute. */ - if (!x86_platform.guest.enc_status_change_finish(addr, numpages, enc)) + ret = x86_platform.guest.enc_status_change_finish(addr, numpages, enc); + if (ret) goto vmm_fail; return 0; vmm_fail: - WARN_ONCE(1, "CPA VMM failure to convert memory (addr=%p, numpages=%d) to %s.\n", - (void *)addr, numpages, enc ? "private" : "shared"); + WARN_ONCE(1, "CPA VMM failure to convert memory (addr=%p, numpages=%d) to %s: %d\n", + (void *)addr, numpages, enc ? "private" : "shared", ret); - return -EIO; + return ret; } static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) -- 2.43.0