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AJvYcCX8nNP3FMFpotZQCvfFDp79J31OQy7UdbA225DbB3AGsV+/Pi0bCLoiGV48ipi1mmelhQr1L/YKsqKxQhzKUPWDnwbVc+v/khRd+Pf5 X-Gm-Message-State: AOJu0YzdBndz+LoYoXiPUQJKKqUgdbLtP+BVYCILumdxDX4TtraanOsy vxhtaML+sWgUnj4v0+v8HSajnY8DwAPwPxPsc43+ot+9gAELSA1oP3yllzQ+6bgk6P5NQIeZ1XK XXzH7kQ== X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:714a:5e65:12a1:603]) (user=irogers job=sendgmr) by 2002:a05:6902:1204:b0:dc6:cd85:bcd7 with SMTP id 3f1490d57ef6-dff153fc8f0mr1152415276.3.1718406262228; Fri, 14 Jun 2024 16:04:22 -0700 (PDT) Date: Fri, 14 Jun 2024 16:01:44 -0700 In-Reply-To: <20240614230146.3783221-1-irogers@google.com> Message-Id: <20240614230146.3783221-37-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240614230146.3783221-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v1 36/37] perf vendor events: Add westmereep-sp counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Type: text/plain; charset="UTF-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers --- .../arch/x86/westmereep-sp/cache.json | 321 ++++++++++++++++++ .../arch/x86/westmereep-sp/counter.json | 7 + .../x86/westmereep-sp/floating-point.json | 28 ++ .../arch/x86/westmereep-sp/frontend.json | 3 + .../arch/x86/westmereep-sp/memory.json | 67 ++++ .../arch/x86/westmereep-sp/other.json | 28 ++ .../arch/x86/westmereep-sp/pipeline.json | 111 ++++++ .../x86/westmereep-sp/virtual-memory.json | 18 + 8 files changed, 583 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json index d025e2c0cf1c..90cb367f5798 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffer", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +563,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +574,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +596,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +607,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +618,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +629,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +640,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +651,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +662,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +684,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +695,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +706,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +717,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +726,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +735,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +744,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +753,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +762,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +780,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +789,7 @@ }, { "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", "PEBS": "1", @@ -705,6 +798,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", "PEBS": "1", @@ -713,6 +807,7 @@ }, { "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", "PEBS": "1", @@ -721,6 +816,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -729,6 +825,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -737,6 +834,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -744,6 +842,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -751,6 +850,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -758,6 +858,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -765,6 +866,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -772,6 +874,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -779,6 +882,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -786,6 +890,7 @@ }, { "BriefDescription": "Offcore uncached memory accesses", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", "SampleAfterValue": "100000", @@ -793,6 +898,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -815,6 +923,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", @@ -823,6 +932,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -830,6 +940,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", @@ -838,6 +949,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -845,6 +957,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -853,6 +966,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -860,6 +974,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +984,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +994,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +1004,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +1014,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1024,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1034,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1044,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1054,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1064,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1074,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1084,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1094,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1104,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1114,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1124,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1134,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1144,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1154,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1164,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1174,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1184,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1194,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1204,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1214,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1224,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1234,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1244,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1254,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1264,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1274,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1284,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1294,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1304,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1314,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1324,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1334,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1344,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1354,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1364,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1374,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1384,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1394,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1404,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1414,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1424,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1434,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1444,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1454,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1464,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1474,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1484,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1494,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1504,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1514,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1524,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1534,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1544,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1554,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1564,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1574,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1584,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1594,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1604,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1614,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1624,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1634,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1644,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1654,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1664,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1674,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1684,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1694,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any location", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1704,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1714,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1724,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1734,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1744,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1754,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1764,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1774,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1784,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1794,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1804,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1814,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1824,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1834,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1844,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1854,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1864,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1874,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1884,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1894,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1904,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1914,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1924,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1934,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1944,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1954,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1964,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +1974,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +1984,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +1994,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +2004,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +2014,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2024,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2034,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2044,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2054,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2064,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2074,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2084,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2094,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2104,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2114,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2124,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2134,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2144,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2154,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2164,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2174,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2184,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2194,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2204,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2214,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2224,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2234,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2244,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2012,6 +2254,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2021,6 +2264,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2030,6 +2274,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2039,6 +2284,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2048,6 +2294,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2057,6 +2304,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2066,6 +2314,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2075,6 +2324,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2084,6 +2334,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2093,6 +2344,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2102,6 +2354,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2111,6 +2364,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2120,6 +2374,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2129,6 +2384,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2138,6 +2394,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2147,6 +2404,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2156,6 +2414,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2165,6 +2424,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2174,6 +2434,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2183,6 +2444,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2192,6 +2454,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2201,6 +2464,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2210,6 +2474,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2219,6 +2484,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2228,6 +2494,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2237,6 +2504,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2246,6 +2514,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2255,6 +2524,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2264,6 +2534,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2273,6 +2544,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2282,6 +2554,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2291,6 +2564,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2300,6 +2574,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2309,6 +2584,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2318,6 +2594,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2327,6 +2604,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2336,6 +2614,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2345,6 +2624,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2354,6 +2634,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2363,6 +2644,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2372,6 +2654,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2381,6 +2664,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2390,6 +2674,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2399,6 +2684,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2408,6 +2694,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2417,6 +2704,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2426,6 +2714,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2435,6 +2724,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2444,6 +2734,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2453,6 +2744,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2462,6 +2754,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2471,6 +2764,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2480,6 +2774,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2489,6 +2784,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2498,6 +2794,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2507,6 +2804,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2516,6 +2814,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2525,6 +2824,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2534,6 +2834,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2543,6 +2844,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2552,6 +2854,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2561,6 +2864,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2570,6 +2874,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2579,6 +2884,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2588,6 +2894,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2597,6 +2904,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2606,6 +2914,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2615,6 +2924,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2624,6 +2934,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2633,6 +2944,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2642,6 +2954,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2651,6 +2964,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2660,6 +2974,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2669,6 +2984,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2678,6 +2994,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2687,6 +3004,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2694,6 +3012,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2701,6 +3020,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2708,6 +3028,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transitions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instructions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instructions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json index b65c5294bcf1..37a69ffe8521 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -118,6 +131,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -163,6 +181,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -172,6 +191,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -181,6 +201,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -190,6 +211,7 @@ }, { "BriefDescription": "Offcore code or data read requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -199,6 +221,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -208,6 +231,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -217,6 +241,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -226,6 +251,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any LLC miss", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -235,6 +261,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the local DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -244,6 +271,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -253,6 +281,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +291,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +301,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +311,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -289,6 +321,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +331,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +341,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +351,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -325,6 +361,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +371,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -343,6 +381,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +391,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +401,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +421,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +431,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +441,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -406,6 +451,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +471,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +481,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +491,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +501,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +511,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +521,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +531,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -487,6 +541,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +551,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +561,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +571,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +581,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -532,6 +591,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -541,6 +601,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -550,6 +611,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -559,6 +621,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -568,6 +631,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -577,6 +641,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -586,6 +651,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -595,6 +661,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json index 488274980564..bcf5bcf637c0 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Loads that partially overlap an earlier store", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "False dependencies due to partial address aliasing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Snoop code requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Snoop data requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Snoop invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Outstanding snoop code requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "Cycles snoop code requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", @@ -142,6 +162,7 @@ }, { "BriefDescription": "Outstanding snoop data requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", @@ -149,6 +170,7 @@ }, { "BriefDescription": "Cycles snoop data requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", @@ -157,6 +179,7 @@ }, { "BriefDescription": "Outstanding snoop invalidate requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", @@ -164,6 +187,7 @@ }, { "BriefDescription": "Cycles snoop invalidate requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", @@ -172,6 +196,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json index a29ed3522779..0267788d9dce 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediciton Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -246,6 +280,7 @@ }, { "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -254,6 +289,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -262,11 +298,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -274,17 +312,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed counter)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -293,6 +334,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -300,6 +342,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -307,6 +350,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -314,6 +358,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -321,6 +366,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -328,6 +374,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -335,6 +382,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -342,6 +390,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -349,11 +398,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -362,6 +413,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -370,6 +422,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -380,6 +433,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -390,6 +444,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -398,6 +453,7 @@ }, { "BriefDescription": "Load operations conflicting with software prefetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -405,6 +461,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -422,6 +480,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -429,6 +488,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -436,6 +496,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -450,6 +512,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -457,6 +520,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -464,6 +528,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -471,6 +536,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -478,6 +544,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -485,6 +552,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -492,6 +560,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -499,6 +568,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -506,6 +576,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -513,6 +584,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -520,6 +592,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -527,6 +600,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -534,6 +608,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -573,6 +652,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -581,6 +661,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -588,6 +669,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -595,6 +677,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -603,6 +686,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -613,6 +697,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -622,6 +707,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -631,6 +717,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -642,6 +729,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -653,6 +741,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -663,6 +752,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -672,6 +762,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -679,6 +770,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -686,6 +778,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -695,6 +788,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -703,6 +797,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -711,6 +806,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -719,6 +815,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -727,6 +824,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -734,6 +832,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -741,6 +840,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -749,6 +849,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -759,6 +860,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -767,6 +869,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -774,6 +877,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -783,6 +887,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -816,6 +924,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -826,6 +935,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -836,6 +946,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json index 80efcfd48239..e7affdf7f41b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -114,6 +130,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -122,6 +139,7 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "PEBS": "1", -- 2.45.2.627.g7a2c4fd464-goog