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AJvYcCUdG02Al1BLgEqA5eeZd1ShtbIEwxLkZM1cIcKe+45fKKSsAaHyPE2iSpBhDNqFIruvuN/upuSW4mqIJildI6dqVvlRWtdReEhr/tEw X-Gm-Message-State: AOJu0YzR8lNYnjFcC0GQQYbtmcxyG2UWd68zD35lofoLa6p8qF/v++Zo Bj35XVusJcBpkHLmwbzsE/bc48Mdmg6+OqXyOmcMBoIa4jUwQZJe3/I/WRXxvjUAoUwQO7OuZfn XDCITdQ== X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:714a:5e65:12a1:603]) (user=irogers job=sendgmr) by 2002:a05:690c:7441:b0:627:a787:abf4 with SMTP id 00721157ae682-6322294d236mr10236297b3.3.1718406253879; Fri, 14 Jun 2024 16:04:13 -0700 (PDT) Date: Fri, 14 Jun 2024 16:01:41 -0700 In-Reply-To: <20240614230146.3783221-1-irogers@google.com> Message-Id: <20240614230146.3783221-34-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240614230146.3783221-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v1 33/37] perf vendor events: Add snowridgex counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Update/remove events as per v1.23: https://github.com/intel/perfmon/commit/9debd874e1b2b0cca42b9ba2342cacaaace= 2f0ce Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/snowridgex/cache.json | 101 + .../arch/x86/snowridgex/counter.json | 47 + .../arch/x86/snowridgex/floating-point.json | 3 + .../arch/x86/snowridgex/frontend.json | 9 + .../arch/x86/snowridgex/memory.json | 40 + .../pmu-events/arch/x86/snowridgex/other.json | 61 + .../arch/x86/snowridgex/pipeline.json | 60 + .../arch/x86/snowridgex/uncore-cache.json | 1548 ++++++++++++++- .../x86/snowridgex/uncore-interconnect.json | 1403 +++++++++++++ .../arch/x86/snowridgex/uncore-io.json | 1743 +++++++++++++++++ .../arch/x86/snowridgex/uncore-memory.json | 103 + .../arch/x86/snowridgex/uncore-power.json | 51 + .../arch/x86/snowridgex/virtual-memory.json | 31 + 14 files changed, 5177 insertions(+), 25 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b5d40fa2a29f..f4adfc157197 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -31,7 +31,7 @@ GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-55-[01234],v1.35,skylakex,core -GenuineIntel-6-86,v1.22,snowridgex,core +GenuineIntel-6-86,v1.23,snowridgex,core GenuineIntel-6-8[CD],v1.15,tigerlake,core GenuineIntel-6-2C,v5,westmereep-dp,core GenuineIntel-6-25,v4,westmereep-sp,core diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/cache.json index c6be60584522..7882dca9d5e1 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", "PublicDescription": "Counts the number of L1D cacheline (dirty) e= victions caused by load misses, stores, and prefetches. Does not count evi= ctions or dirty writebacks caused by snoops. Does not count a replacement = unless a (dirty) line was written back.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ANY", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the total number of L2 Cache accesses.= Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts the total number of L2 Cache Accesses= , includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/= L2 Prefetches only. Counts on a per core basis.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a hit. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.HIT", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a hit from a front door request only (does not include rejects = or recycles), Counts on a per core basis.", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a miss. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a miss from a front door request only (does not include rejects= or recycles). Counts on a per core basis.", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that m= iss the L2 and get rejected. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.REJECTS", "PublicDescription": "Counts the number of L2 Cache accesses that = miss the L2 and get BBL reject short and long rejects (includes those coun= ted in L2_reject_XQ.any). Counts on a per core basis.", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -94,6 +106,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", "SampleAfterValue": "200003", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", "SampleAfterValue": "200003", @@ -116,6 +131,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "SampleAfterValue": "200003", @@ -123,6 +139,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", @@ -131,6 +148,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a store buffer being full.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", "SampleAfterValue": "200003", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -147,6 +166,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache, in which a snoop was required and modified data was for= warded from another core or module.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", @@ -156,6 +176,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -165,6 +186,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -183,6 +206,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", @@ -201,6 +226,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL", @@ -211,6 +237,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -231,6 +259,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", @@ -249,6 +279,7 @@ }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -258,6 +289,7 @@ }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -267,6 +299,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -276,6 +309,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -285,6 +319,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -303,6 +339,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -312,6 +349,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -321,6 +359,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -330,6 +369,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -339,6 +379,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -348,6 +389,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -357,6 +399,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -366,6 +409,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -375,6 +419,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -384,6 +429,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -393,6 +439,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -402,6 +449,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD"= , "MSRIndex": "0x1a6,0x1a7", @@ -411,6 +459,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -420,6 +469,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -429,6 +479,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED"= , "MSRIndex": "0x1a6,0x1a7", @@ -438,6 +489,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", @@ -448,6 +500,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", @@ -458,6 +511,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", @@ -468,6 +522,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -478,6 +533,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", @@ -488,6 +544,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", @@ -498,6 +555,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -507,6 +565,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -516,6 +575,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -525,6 +585,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -543,6 +605,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -552,6 +615,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -561,6 +625,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -570,6 +635,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -579,6 +645,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -588,6 +655,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -597,6 +665,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -606,6 +675,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -615,6 +685,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +695,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -633,6 +705,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -642,6 +715,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -651,6 +725,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -660,6 +735,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -669,6 +745,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -678,6 +755,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -687,6 +765,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -696,6 +775,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -705,6 +785,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +795,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -723,6 +805,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -732,6 +815,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -741,6 +825,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -750,6 +835,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -759,6 +845,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -768,6 +855,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -777,6 +865,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -786,6 +875,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -795,6 +885,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -804,6 +895,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -813,6 +905,7 @@ }, { "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -822,6 +915,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -831,6 +925,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -840,6 +935,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -849,6 +945,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -858,6 +955,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -867,6 +965,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +975,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -885,6 +985,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/counter.json b/tools= /perf/pmu-events/arch/x86/snowridgex/counter.json new file mode 100644 index 000000000000..5ae30dc3c1ac --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/snowridgex/counter.json @@ -0,0 +1,47 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": 1, + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json = b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json index 88522244b760..79a4beba4b78 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.FPDIV", "PublicDescription": "Counts the number of cycles the floating poi= nt divider is busy. Does not imply a stall waiting for the divider.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/frontend.json index 5ba998e06592..6d131ed90242 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a condit= ional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to an indir= ect branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.INDIRECT", "SampleAfterValue": "200003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a return= branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.UNCOND", "SampleAfterValue": "200003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of times a decode restricti= on reduces the decode throughput due to wrong instruction length prediction= .", + "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "SampleAfterValue": "200003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", @@ -52,6 +59,7 @@ }, { "BriefDescription": "Counts the number of instruction cache hits."= , + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts the number of instruction cache misses= .", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/= perf/pmu-events/arch/x86/snowridgex/memory.json index c02eb0e836ad..34306ec24e9b 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of misaligned load uops tha= t are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of misaligned store uops th= at are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", @@ -106,6 +118,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/other.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/other.json index fefbc383b840..57613207f7ad 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.SELF_LOCKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EdgeDetect": "1", "EventCode": "0x63", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock issued by other cores.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.BLOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock issued by other cores. Counts on a per c= ore basis.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.BLOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", @@ -25,6 +28,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.LOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock it issued.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.LOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock it issued. Counts on a per core basis.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of bus locks a core issued = its self (e.g. lock to UC or Split Lock) and does not include cache locks."= , + "Counter": "0,1,2,3", "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.SELF_LOCKS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_DRAM_HIT", @@ -57,6 +64,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_L2_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_L2_HIT", @@ -65,6 +73,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_LLC_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_LLC_HIT", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.MASKED", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= there are pending interrupts while interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of hardware interrupts rece= ived by the processor.", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.RECEIVED", "SampleAfterValue": "203", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Counts all code reads that have any type of r= esponse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -141,6 +158,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.OUTSTANDING", "MSRIndex": "0x1a6", @@ -150,6 +168,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -159,6 +178,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -168,6 +188,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -177,6 +198,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -186,6 +208,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -213,6 +238,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", @@ -223,6 +249,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", @@ -233,6 +260,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", @@ -243,6 +271,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", @@ -253,6 +282,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +292,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +302,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +312,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -289,6 +322,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +332,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +342,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +352,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -325,6 +362,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +372,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency)."= , + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -343,6 +382,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +392,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +402,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +412,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +422,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +432,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +442,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -406,6 +452,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +462,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +472,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +482,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +492,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +502,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +512,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +522,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +532,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.OUTSTANDING", "MSRIndex": "0x1a6", @@ -487,6 +542,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +552,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +572,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +582,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -532,6 +592,7 @@ }, { "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/pipeline.json index c483c0838e08..e4e7902c1162 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "Counts the total number of BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", @@ -142,6 +160,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -165,6 +186,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", @@ -172,6 +194,7 @@ }, { "BriefDescription": "Counts the number of cycles the integer divid= er is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", "PublicDescription": "Counts the number of cycles the integer divi= der is busy. Does not imply a stall waiting for the divider.", @@ -180,6 +203,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", @@ -188,6 +212,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed.", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -196,6 +221,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "1", @@ -204,6 +230,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked for any of the following reasons: DTLB miss, address alias, store f= orward or data unknown (includes memory disambiguation blocks and ESP consu= ming load blocks).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL", "PEBS": "1", @@ -212,6 +239,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", @@ -220,6 +248,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "1", @@ -228,12 +257,14 @@ }, { "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", "SampleAfterValue": "20003" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -241,6 +272,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -248,6 +280,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -255,6 +288,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", @@ -263,6 +297,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -270,6 +305,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -277,6 +313,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -284,6 +321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", @@ -292,12 +330,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -305,6 +345,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -312,6 +353,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -319,6 +361,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -326,6 +369,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -333,6 +377,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -340,6 +385,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", @@ -348,12 +394,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", @@ -362,6 +410,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", @@ -370,6 +419,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -377,6 +427,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -384,6 +435,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", @@ -392,6 +444,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -399,6 +452,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -406,6 +460,7 @@ }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", @@ -413,6 +468,7 @@ }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -420,6 +476,7 @@ }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -427,6 +484,7 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", @@ -435,6 +493,7 @@ }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", @@ -444,6 +503,7 @@ }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json index 4090e4da1bd0..7551fb91a9d7 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.= ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_READ", "Filter": "config1=3D0x40040e33", @@ -11,6 +12,7 @@ }, { "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts= .ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "config1=3D0x40041e33", @@ -21,6 +23,7 @@ }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "config1=3D0x40e33", @@ -31,6 +34,7 @@ }, { "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "config1=3D0x41833", @@ -42,6 +46,7 @@ }, { "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "config1=3D0x41a33", @@ -53,8 +58,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -62,8 +69,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -71,8 +80,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -80,8 +91,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -89,8 +102,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -98,8 +113,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -107,8 +124,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -116,8 +135,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -125,8 +146,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -134,8 +157,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -143,8 +168,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -152,8 +179,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -161,8 +190,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -170,8 +201,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -179,8 +212,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -188,8 +223,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -197,8 +234,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -206,8 +245,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -215,8 +256,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -224,8 +267,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -233,8 +278,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -242,8 +289,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -251,8 +300,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -260,8 +311,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -269,8 +322,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -278,8 +333,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -287,8 +344,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -296,8 +355,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -305,8 +366,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -314,8 +377,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -323,8 +388,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -332,8 +399,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -341,8 +410,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -350,8 +421,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -359,8 +432,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -368,8 +443,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -377,8 +454,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -386,8 +465,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -395,8 +476,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -404,8 +487,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -413,8 +498,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -422,8 +509,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -431,8 +520,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -440,8 +531,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -449,8 +542,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -458,8 +553,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -467,8 +564,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -476,8 +575,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -485,8 +586,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -494,8 +597,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -503,8 +608,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -512,8 +619,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -521,8 +630,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -530,8 +641,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -539,8 +652,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -548,8 +663,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -557,8 +674,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -566,8 +685,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -575,8 +696,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -584,8 +707,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -593,8 +718,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -602,8 +729,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -611,8 +740,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -620,8 +751,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -629,8 +762,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -638,8 +773,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -647,8 +784,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -656,8 +795,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -665,8 +806,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -674,8 +817,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -683,8 +828,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -692,8 +839,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -701,8 +850,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -710,8 +861,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -719,8 +872,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -728,8 +883,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -737,8 +894,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -746,8 +905,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -755,8 +916,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -764,8 +927,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -773,8 +938,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -782,8 +949,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -791,8 +960,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -800,8 +971,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -809,8 +982,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -818,8 +993,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -827,8 +1004,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -836,8 +1015,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -845,8 +1026,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", "UMask": "0x2", @@ -854,8 +1037,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", "UMask": "0x4", @@ -863,8 +1048,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", "UMask": "0x1", @@ -872,12 +1059,14 @@ }, { "BriefDescription": "Uncore cache clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", @@ -885,8 +1074,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0xf2", @@ -894,8 +1085,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", "UMask": "0xf1", @@ -903,8 +1096,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", @@ -912,8 +1107,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", "UMask": "0x41", @@ -921,8 +1118,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction"= , + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", @@ -930,8 +1129,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", "UMask": "0x81", @@ -939,8 +1140,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x22", @@ -948,8 +1151,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x21", @@ -957,104 +1162,130 @@ }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counter 0 Occupancy : Since occupancy counts= can only be captured in the Cbo's 0 counter, this event allows a user to c= apture occupancy related information by filtering the Cb0 occupancy count c= aptured in Counter 0. The filtering available is found in the control reg= ister - threshold, invert and edge detect. E.g. setting threshold to 1 ca= n effectively monitor how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1062,8 +1293,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1071,8 +1304,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1080,8 +1315,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1089,8 +1326,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1098,8 +1337,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1107,8 +1348,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1116,8 +1359,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1125,8 +1370,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1134,8 +1381,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1143,8 +1392,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1152,8 +1403,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1161,8 +1414,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1170,8 +1425,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1179,8 +1436,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1188,8 +1447,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1197,8 +1458,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1206,8 +1469,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1215,8 +1480,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1224,8 +1491,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1233,8 +1502,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1242,8 +1513,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1251,8 +1524,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1260,8 +1535,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1269,8 +1546,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1278,8 +1557,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1287,6 +1568,7 @@ }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -1296,8 +1578,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", "UMask": "0x2", @@ -1305,6 +1589,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -1314,8 +1599,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", "UMask": "0x4", @@ -1323,8 +1610,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", "UMask": "0x2", @@ -1332,8 +1621,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", "UMask": "0x8", @@ -1341,8 +1632,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1fffff", @@ -1350,25 +1643,31 @@ }, { "BriefDescription": "Cache Lookups : All Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Any local or remote transaction to the LLC, includi= ng prefetch.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bd0ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Code Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bd0ff", @@ -1376,16 +1675,20 @@ }, { "BriefDescription": "Cache Lookups : CRd Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote CRd transactions to the LLC. This = includes CRd prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Code Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bd001", @@ -1393,23 +1696,28 @@ }, { "BriefDescription": "Cache Lookups : Local request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Any local transaction to the LLC, including prefe= tches from the Core", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -1419,25 +1727,31 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1fc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Data Read Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Request Filter : C= ounts the number of times the LLC was accessed - this includes code, data, = prefetches and hints coming from L2. This has numerous filters available. = Note the non-standard filtering equation. This event will count requests = that lookup the cache multiple times with multiple increments. One must AL= WAYS select a state or states (in the umask field) to match. Otherwise, th= e event will count nothing. : Read transactions.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bc101", @@ -1445,17 +1759,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x841ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Exclusive State", "UMask": "0x20", @@ -1463,8 +1781,10 @@ }, { "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Forward State", "UMask": "0x80", @@ -1472,8 +1792,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests"= , + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a44ff", @@ -1481,16 +1803,20 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush or Invalidate Filter := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Miss", "UMask": "0x1", @@ -1498,16 +1824,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed locally Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally F= ilter : Counts the number of times the LLC was accessed - this includes cod= e, data, prefetches and hints coming from L2. This has numerous filters av= ailable. Note the non-standard filtering equation. This event will count = requests that lookup the cache multiple times with multiple increments. On= e must ALWAYS select a state or states (in the umask field) to match. Othe= rwise, the event will count nothing. : Transaction whose address resides in= the local MC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Modified State", "UMask": "0x40", @@ -1515,8 +1845,10 @@ }, { "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1fe001", @@ -1524,16 +1856,20 @@ }, { "BriefDescription": "Cache Lookups : Write Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Writeback transactions to the LLC This includes = all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS select a state= or states (in the umask field) to match. Otherwise, the event will count = nothing.", "UMask": "0x1bd9ff", @@ -1541,8 +1877,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Locally HOMed : Counts the number of times the LLC was accessed - this= includes code, data, prefetches and hints coming from L2. This has numero= us filters available. Note the non-standard filtering equation. This even= t will count requests that lookup the cache multiple times with multiple in= crements. One must ALWAYS select a state or states (in the umask field) to= match. Otherwise, the event will count nothing.", "UMask": "0x9d9ff", @@ -1550,8 +1888,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Remotely HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0x11d9ff", @@ -1559,8 +1899,10 @@ }, { "BriefDescription": "Cache Lookups : Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Read Misses : Counts the num= ber of times the LLC was accessed - this includes code, data, prefetches an= d hints coming from L2. This has numerous filters available. Note the non= -standard filtering equation. This event will count requests that lookup t= he cache multiple times with multiple increments. One must ALWAYS select a= state or states (in the umask field) to match. Otherwise, the event will = count nothing.", "UMask": "0x1bd901", @@ -1568,8 +1910,10 @@ }, { "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS select a state or states (in the umask field) to match. Otherwise, t= he event will count nothing.", "UMask": "0xbd901", @@ -1577,8 +1921,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "UMask": "0x13d901", @@ -1586,8 +1932,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely requested Read or Sn= oop Misses that are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM= ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely requested Read or S= noop Misses that are Remotely HOMed : Counts the number of times the LLC wa= s accessed - this includes code, data, prefetches and hints coming from L2.= This has numerous filters available. Note the non-standard filtering equ= ation. This event will count requests that lookup the cache multiple times= with multiple increments. One must ALWAYS select a state or states (in th= e umask field) to match. Otherwise, the event will count nothing.", "UMask": "0x161901", @@ -1595,8 +1943,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely Requested Reads that= are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely Requested Reads tha= t are Locally HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0xa19ff", @@ -1604,8 +1954,10 @@ }, { "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filt= er", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Fil= ter : Counts the number of times the LLC was accessed - this includes code,= data, prefetches and hints coming from L2. This has numerous filters avai= lable. Note the non-standard filtering equation. This event will count re= quests that lookup the cache multiple times with multiple increments. One = must ALWAYS select a state or states (in the umask field) to match. Otherw= ise, the event will count nothing.", "UMask": "0x1bd90e", @@ -1613,8 +1965,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1bc8ff", @@ -1622,16 +1976,20 @@ }, { "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote RFO transactions to the LLC. This = includes RFO prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : RFO Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bc801", @@ -1639,17 +1997,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x888ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Shared State", "UMask": "0x10", @@ -1657,8 +2019,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Exclusive State", "UMask": "0x4", @@ -1666,8 +2030,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit HitMe State", "UMask": "0x8", @@ -1675,8 +2041,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Shared State", "UMask": "0x2", @@ -1684,8 +2052,10 @@ }, { "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "UMask": "0x1a42ff", @@ -1693,15 +2063,18 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x842ff", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : All Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.ALL", "PerPkg": "1", @@ -1711,8 +2084,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x2", @@ -1720,8 +2095,10 @@ }, { "BriefDescription": "Lines Victimized : Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - All Lines : Count= s the number of lines that were victimized on a fill. This can be filtered= by the state that the line was in.", "UMask": "0x200f", @@ -1729,8 +2106,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in E State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2002", @@ -1738,8 +2117,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in M State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2001", @@ -1747,16 +2128,20 @@ }, { "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : Local - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in S State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2004", @@ -1764,8 +2149,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x1", @@ -1773,8 +2160,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x4", @@ -1782,8 +2171,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", "UMask": "0x20", @@ -1791,8 +2182,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", "UMask": "0x10", @@ -1800,8 +2193,10 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x8", @@ -1809,8 +2204,10 @@ }, { "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", "UMask": "0x1", @@ -1818,8 +2215,10 @@ }, { "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", @@ -1827,64 +2226,80 @@ }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x4", @@ -1892,8 +2307,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x10", @@ -1901,8 +2318,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x2", @@ -1910,8 +2329,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x8", @@ -1919,88 +2340,110 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x80", @@ -2008,8 +2451,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x1", @@ -2017,104 +2462,100 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", "UMask": "0x1", @@ -2122,8 +2563,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", "UMask": "0x2", @@ -2131,40 +2574,50 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", "UMask": "0x4", @@ -2172,8 +2625,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", "UMask": "0x8", @@ -2181,8 +2636,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", @@ -2190,8 +2647,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", @@ -2199,8 +2658,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 6 only.", "UMask": "0x40", @@ -2208,8 +2669,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 7 only.", "UMask": "0x80", @@ -2217,24 +2680,30 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and remote INVI= TOE requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", "UMask": "0x30", @@ -2242,6 +2711,7 @@ }, { "BriefDescription": "Local read requests that miss the SF/LLC and = remote read requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -2251,6 +2721,7 @@ }, { "BriefDescription": "Local write requests that miss the SF/LLC and= remote write requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -2260,8 +2731,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -2269,8 +2742,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -2278,8 +2753,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -2287,8 +2764,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -2296,8 +2775,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -2305,8 +2786,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -2314,8 +2797,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -2323,8 +2808,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -2332,8 +2819,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -2341,95 +2830,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_CHA_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", @@ -2437,8 +2950,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", "UMask": "0x2", @@ -2446,8 +2961,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", @@ -2455,8 +2972,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", @@ -2464,8 +2983,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2473,8 +2994,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2482,8 +3005,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2491,8 +3016,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2500,8 +3027,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2509,8 +3038,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2518,8 +3049,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2527,8 +3060,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -2536,16 +3071,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", "UMask": "0x1", @@ -2553,16 +3092,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2570,24 +3113,30 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2595,16 +3144,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2612,8 +3165,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2621,8 +3176,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -2630,8 +3187,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2639,8 +3198,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2648,8 +3209,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2657,8 +3220,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2666,8 +3231,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -2675,8 +3242,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2684,8 +3253,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2693,8 +3264,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -2702,8 +3275,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2711,8 +3286,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2720,8 +3297,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2729,8 +3308,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2738,8 +3319,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -2747,8 +3330,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2756,8 +3341,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2765,8 +3352,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2774,8 +3363,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2783,8 +3374,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", @@ -2792,8 +3385,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", "UMask": "0x1", @@ -2801,8 +3396,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", "UMask": "0x2", @@ -2810,8 +3407,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", "UMask": "0x40", @@ -2819,8 +3418,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2828,8 +3429,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2837,8 +3440,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", "UMask": "0x4", @@ -2846,8 +3451,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", "UMask": "0x8", @@ -2855,8 +3462,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", "UMask": "0x80", @@ -2864,8 +3473,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", "UMask": "0x40", @@ -2873,8 +3484,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", "UMask": "0x1", @@ -2882,8 +3495,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", "UMask": "0x2", @@ -2891,8 +3506,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", "UMask": "0x20", @@ -2900,8 +3517,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", "UMask": "0x4", @@ -2909,8 +3528,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", "UMask": "0x80", @@ -2918,8 +3539,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", "UMask": "0x8", @@ -2927,8 +3550,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", "UMask": "0x10", @@ -2936,8 +3561,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2945,8 +3572,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2954,8 +3583,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2963,8 +3594,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2972,8 +3605,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2981,8 +3616,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2990,8 +3627,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2999,8 +3638,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -3008,16 +3649,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", "UMask": "0x1", @@ -3025,16 +3670,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3042,16 +3691,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -3059,8 +3712,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3068,16 +3723,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3085,8 +3744,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3094,8 +3755,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", @@ -3103,8 +3766,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3112,8 +3777,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3121,8 +3788,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3130,8 +3799,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0"= , + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3139,8 +3810,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", "UMask": "0x80", @@ -3148,8 +3821,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)"= , "UMask": "0x40", @@ -3157,8 +3832,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -3166,8 +3843,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x2", @@ -3175,8 +3854,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3184,8 +3865,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x4", @@ -3193,8 +3876,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -3202,8 +3887,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3211,8 +3898,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x10", @@ -3220,8 +3909,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3229,8 +3920,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -3238,8 +3931,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -3247,8 +3942,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3256,8 +3953,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -3265,8 +3964,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -3274,8 +3975,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3283,8 +3986,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -3292,8 +3997,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -3301,8 +4008,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -3310,8 +4019,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -3319,8 +4030,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3328,8 +4041,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -3337,8 +4052,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -3346,8 +4063,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -3355,8 +4074,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3364,8 +4085,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -3373,8 +4096,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -3382,8 +4107,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -3391,8 +4118,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3400,8 +4129,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -3409,8 +4140,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -3418,8 +4151,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -3427,8 +4162,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -3436,16 +4173,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "CHA" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3453,8 +4194,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -3462,8 +4205,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -3471,8 +4216,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -3480,8 +4227,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -3489,8 +4238,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3498,8 +4249,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -3507,8 +4260,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -3516,8 +4271,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -3525,8 +4282,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3534,8 +4293,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -3543,8 +4304,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -3552,8 +4315,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -3561,8 +4326,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -3570,8 +4337,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3579,8 +4348,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -3588,8 +4359,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -3597,8 +4370,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -3606,6 +4381,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", @@ -3615,6 +4391,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", @@ -3624,6 +4401,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", @@ -3633,8 +4411,10 @@ }, { "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", "UMask": "0x1", @@ -3642,8 +4422,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Local Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f broadcast snoops issued by the HA responding to local requests", "UMask": "0x10", @@ -3651,8 +4433,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA responding to local requests", "UMask": "0x40", @@ -3660,8 +4444,10 @@ }, { "BriefDescription": "Snoops Sent : Snoops sent for Local Requests"= , + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Snoops sent for Local Requests= : Counts the number of snoops issued by the HA. : Counts the number of bro= adcast or directed snoops issued by the HA responding to local requests", "UMask": "0x4", @@ -3669,8 +4455,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", "UMask": "0x40", @@ -3678,8 +4466,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", "UMask": "0x80", @@ -3687,8 +4477,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", "UMask": "0x20", @@ -3696,8 +4488,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", "UMask": "0x1", @@ -3705,8 +4499,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -3714,8 +4510,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", "UMask": "0x2", @@ -3723,8 +4521,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its currently copy. This is c= ommon for data and code reads that hit in a remote socket in E or F state."= , "UMask": "0x8", @@ -3732,8 +4532,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", "UMask": "0x10", @@ -3741,56 +4543,70 @@ }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3798,8 +4614,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3807,8 +4625,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3816,8 +4636,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3825,8 +4647,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3834,8 +4658,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3843,8 +4669,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3852,8 +4680,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3861,8 +4691,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3870,8 +4702,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3879,8 +4713,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3888,8 +4724,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3897,8 +4735,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3906,8 +4746,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3915,8 +4757,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3924,8 +4768,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3933,8 +4779,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3942,8 +4790,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3951,8 +4801,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3960,8 +4812,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3969,8 +4823,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3978,8 +4834,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3987,8 +4845,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3996,8 +4856,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4005,8 +4867,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4014,8 +4878,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4023,8 +4889,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4032,8 +4900,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -4041,8 +4911,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -4050,8 +4922,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -4059,8 +4933,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -4068,8 +4944,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4077,8 +4955,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4086,8 +4966,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4095,8 +4977,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4104,8 +4988,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4113,8 +4999,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4122,8 +5010,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4131,8 +5021,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4140,8 +5032,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4149,8 +5043,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4158,8 +5054,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4167,8 +5065,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4176,8 +5076,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4185,8 +5087,10 @@ }, { "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0xc001ffff", @@ -4194,24 +5098,30 @@ }, { "BriefDescription": "TOR Inserts : DDR4 Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DDR4 Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts. : TOR allocation occurred as a result of SF/LLC e= victions (came from the ISMQ)", "UMask": "0x2", @@ -4219,14 +5129,17 @@ }, { "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All requests from iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -4236,6 +5149,7 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -4245,8 +5159,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores"= , + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4254,6 +5170,7 @@ }, { "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -4263,8 +5180,10 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4272,8 +5191,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -4281,6 +5202,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", "PerPkg": "1", @@ -4290,6 +5212,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -4299,6 +5222,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -4308,6 +5232,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -4317,6 +5242,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -4326,8 +5252,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837fd01", @@ -4335,6 +5263,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -4344,6 +5273,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -4353,6 +5283,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -4362,6 +5293,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -4371,6 +5303,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -4380,6 +5313,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -4389,6 +5323,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -4398,8 +5333,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc837fe01", @@ -4407,6 +5344,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -4416,6 +5354,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", @@ -4425,6 +5364,7 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", @@ -4434,6 +5374,7 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", "PerPkg": "1", @@ -4443,6 +5384,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -4452,6 +5394,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -4461,6 +5404,7 @@ }, { "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", @@ -4470,6 +5414,7 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", @@ -4479,6 +5424,7 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", @@ -4488,6 +5434,7 @@ }, { "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", @@ -4497,6 +5444,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -4506,6 +5454,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -4515,8 +5464,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc3fff01", @@ -4524,8 +5475,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc37ff01", @@ -4533,8 +5486,10 @@ }, { "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc2fff01", @@ -4542,8 +5497,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -4551,8 +5508,10 @@ }, { "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc67ff01", @@ -4560,8 +5519,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc86fff01", @@ -4569,8 +5530,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc867ff01", @@ -4578,6 +5541,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", @@ -4587,8 +5551,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices"= , + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -4596,6 +5562,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -4605,6 +5572,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -4614,6 +5582,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -4623,6 +5592,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -4632,8 +5602,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= hit the LLC : Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -4641,6 +5613,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -4650,6 +5623,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -4659,6 +5633,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -4668,6 +5643,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -4677,6 +5653,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -4686,6 +5663,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -4695,8 +5673,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= missed the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -4704,6 +5684,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices"= , + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -4713,8 +5694,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Co= unts the number of entries successfully inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -4722,8 +5705,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -4731,8 +5716,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts. : From an iA Core", "UMask": "0x1", @@ -4740,8 +5727,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "UMask": "0x10", @@ -4749,24 +5738,30 @@ }, { "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts. : All locally initiated requests", "UMask": "0xc000ff05", @@ -4774,8 +5769,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally initiated requests from iA Cores", "UMask": "0xc000ff01", @@ -4783,8 +5780,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally generated IO traffic", "UMask": "0xc000ff04", @@ -4792,64 +5791,80 @@ }, { "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent. Do= es not include addressless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests such = as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event. Does not include addressless requests such as locks and interrupts= .", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. Does not include addressless requests such as lo= cks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -4857,8 +5872,10 @@ }, { "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent. Does not include addressless requests such a= s locks and interrupts.", "UMask": "0x20", @@ -4866,16 +5883,20 @@ }, { "BriefDescription": "TOR Occupancy : DDR4 Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts. : TOR allocation occurred as a = result of SF/LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -4883,14 +5904,17 @@ }, { "BriefDescription": "TOR Occupancy : Just Hits", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4900,8 +5924,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores"= , + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc8c7ff01", @@ -4909,8 +5935,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4918,6 +5946,7 @@ }, { "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -4927,8 +5956,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4936,8 +5967,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -4945,6 +5978,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", "PerPkg": "1", @@ -4954,6 +5988,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -4963,6 +5998,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4972,8 +6008,10 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80ffd01", @@ -4981,8 +6019,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88ffd01", @@ -4990,8 +6030,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that hit the LLC : For each cycle, this event accumulates = the number of valid entries in the TOR that match qualifications specified = by the subevent. Does not include addressless requests such as locks an= d interrupts.", "UMask": "0xc837fd01", @@ -4999,6 +6041,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -5008,6 +6051,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -5017,8 +6061,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc807fd01", @@ -5026,8 +6072,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc887fd01", @@ -5035,6 +6083,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -5044,6 +6093,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -5053,8 +6103,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc88ffe01", @@ -5062,8 +6114,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that missed the LLC : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc837fe01", @@ -5071,6 +6125,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -5080,8 +6135,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC : For each cycle, this event accumulates the numbe= r of valid entries in the TOR that match qualifications specified by the su= bevent. Does not include addressless requests such as locks and interru= pts.", "UMask": "0xc8a7fe01", @@ -5089,8 +6146,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc867fe01", @@ -5098,8 +6157,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86ffe01", @@ -5107,6 +6168,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -5116,8 +6178,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc887fe01", @@ -5125,8 +6189,10 @@ }, { "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -5134,8 +6200,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -5143,8 +6211,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -5152,8 +6222,10 @@ }, { "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -5161,6 +6233,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -5170,8 +6243,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores"= , + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc887ff01", @@ -5179,8 +6254,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -5188,8 +6265,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -5197,8 +6276,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -5206,6 +6287,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices"= , + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", @@ -5215,8 +6297,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -5224,6 +6308,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", @@ -5233,8 +6318,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fd04", @@ -5242,8 +6329,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that hit the LLC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "UMask": "0xcd43fd04", @@ -5251,8 +6340,10 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts."= , "UMask": "0xc8f3fd04", @@ -5260,8 +6351,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -5269,8 +6362,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc43ff04", @@ -5278,8 +6373,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "UMask": "0xcd43ff04", @@ -5287,6 +6384,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", @@ -5296,8 +6394,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fe04", @@ -5305,8 +6405,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xcd43fe04", @@ -5314,6 +6416,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -5323,8 +6426,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -5332,6 +6437,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -5341,8 +6447,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -5350,8 +6458,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices"= , + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -5359,8 +6469,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts. : From an iA Core", "UMask": "0x1", @@ -5368,8 +6480,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0x10", @@ -5377,24 +6491,30 @@ }, { "BriefDescription": "TOR Occupancy : Just ISOC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Local Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. Does not include addre= ssless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts. : All locally initiated= requests", "UMask": "0xc000ff05", @@ -5402,8 +6522,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally initiated reques= ts from iA Cores", "UMask": "0xc000ff01", @@ -5411,8 +6533,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally generated IO tra= ffic", "UMask": "0xc000ff04", @@ -5420,64 +6544,80 @@ }, { "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Misses", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMCFG Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NonCoherent", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NotNearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. Does not include addressl= ess requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -5485,8 +6625,10 @@ }, { "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", "UMask": "0x20", @@ -5494,8 +6636,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5503,8 +6647,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -5512,8 +6658,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -5521,8 +6669,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5530,8 +6680,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -5539,8 +6691,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -5548,8 +6702,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5557,8 +6713,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -5566,8 +6724,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -5575,8 +6735,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -5584,8 +6746,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -5593,8 +6757,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5602,8 +6768,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -5611,8 +6779,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -5620,8 +6790,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -5629,8 +6801,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5638,8 +6812,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -5647,8 +6823,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -5656,8 +6834,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -5665,8 +6845,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -5674,8 +6856,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5683,8 +6867,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -5692,8 +6878,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -5701,8 +6889,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -5710,8 +6900,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5719,8 +6911,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -5728,8 +6922,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -5737,8 +6933,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -5746,8 +6944,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -5755,8 +6955,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5764,8 +6966,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -5773,8 +6977,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -5782,8 +6988,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -5791,8 +6999,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5800,8 +7010,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -5809,8 +7021,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -5818,8 +7032,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -5827,8 +7043,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -5836,8 +7054,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5845,8 +7065,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -5854,8 +7076,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -5863,8 +7087,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -5872,8 +7098,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -5881,8 +7109,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -5890,8 +7120,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -5899,8 +7131,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -5908,8 +7142,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -5917,8 +7153,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -5926,8 +7164,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -5935,8 +7175,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -5944,8 +7186,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -5953,8 +7197,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5962,8 +7208,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -5971,8 +7219,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -5980,8 +7230,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -5989,8 +7241,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -5998,8 +7252,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6007,8 +7263,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -6016,8 +7274,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -6025,8 +7285,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -6034,8 +7296,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -6043,8 +7307,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -6052,8 +7318,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -6061,8 +7329,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -6070,8 +7340,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -6079,8 +7351,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -6088,8 +7362,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -6097,8 +7373,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -6106,8 +7384,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -6115,8 +7395,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -6124,8 +7406,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -6133,8 +7417,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -6142,8 +7428,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -6151,8 +7439,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -6160,8 +7450,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -6169,8 +7461,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -6178,8 +7472,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -6187,8 +7483,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -6196,8 +7494,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -6205,8 +7505,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -6214,8 +7516,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6223,8 +7527,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -6232,8 +7538,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6241,8 +7549,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6250,8 +7560,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -6259,8 +7571,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -6268,8 +7582,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -6277,8 +7593,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6286,8 +7604,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6295,8 +7615,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -6304,8 +7626,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -6313,8 +7637,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6322,8 +7648,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6331,8 +7659,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -6340,8 +7670,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -6349,8 +7681,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -6358,8 +7692,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -6367,8 +7703,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6376,8 +7714,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6385,8 +7725,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -6394,8 +7736,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -6403,8 +7747,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6412,8 +7758,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -6421,8 +7769,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -6430,8 +7780,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -6439,8 +7791,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6448,8 +7802,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -6457,8 +7813,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -6466,8 +7824,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -6475,8 +7835,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -6484,8 +7846,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -6493,8 +7857,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -6502,8 +7868,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -6511,8 +7879,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -6520,8 +7890,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -6529,8 +7901,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -6538,8 +7912,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6547,8 +7923,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -6556,8 +7934,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -6565,8 +7945,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6574,8 +7956,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -6583,8 +7967,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -6592,8 +7978,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -6601,8 +7989,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6610,8 +8000,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -6619,8 +8011,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -6628,8 +8022,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -6637,8 +8033,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -6646,8 +8044,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -6655,8 +8055,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -6664,8 +8066,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -6673,8 +8077,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -6682,8 +8088,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -6691,8 +8099,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -6700,8 +8110,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -6709,8 +8121,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6718,8 +8132,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6727,8 +8143,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6736,8 +8154,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6745,8 +8165,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6754,8 +8176,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6763,8 +8187,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6772,8 +8198,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6781,8 +8209,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6790,8 +8220,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6799,8 +8231,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6808,8 +8242,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6817,8 +8253,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6826,8 +8264,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6835,8 +8275,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -6844,8 +8286,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -6853,8 +8297,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -6862,8 +8308,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -6871,8 +8319,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6880,8 +8330,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6889,8 +8341,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6898,8 +8352,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6907,8 +8363,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", "UMask": "0x1", @@ -6916,8 +8374,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", "UMask": "0x2", @@ -6925,8 +8385,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", "UMask": "0x1", @@ -6934,8 +8396,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", "UMask": "0x2", @@ -6943,40 +8407,50 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", "UMask": "0x4", @@ -6984,8 +8458,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", "UMask": "0x8", @@ -6993,8 +8469,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", "UMask": "0x10", @@ -7002,8 +8480,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", "UMask": "0x20", @@ -7011,8 +8491,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 6 only.", "UMask": "0x40", @@ -7020,8 +8502,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 7 only.", "UMask": "0x80", @@ -7029,24 +8513,30 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x8", @@ -7054,8 +8544,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x4", @@ -7063,8 +8555,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x80", @@ -7072,8 +8566,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x40", @@ -7081,8 +8577,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", "UMask": "0x1", @@ -7090,8 +8588,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", "UMask": "0x10", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json index 7cc3635b118b..88ee90b8a2d9 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total Write Cache Occupancy : Any Source", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Any Source : A= ccumulates the number of reads and writes that are outstanding in the uncor= e in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRI= TE_OCCUPANCY events. : Tracks all requests from any source port.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "Total Write Cache Occupancy : Snoops", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Snoops : Accum= ulates the number of reads and writes that are outstanding in the uncore in= each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_O= CCUPANCY events.", "UMask": "0x2", @@ -19,6 +23,7 @@ }, { "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", "EventCode": "0x0f", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", @@ -28,6 +33,7 @@ }, { "BriefDescription": "Clockticks of the IO coherency tracker (IRP)"= , + "Counter": "0,1", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -35,8 +41,10 @@ }, { "BriefDescription": "Coherent Ops : CLFlush", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Coherent Ops : CLFlush : Counts the number o= f coherency related operations serviced by the IRP", "UMask": "0x80", @@ -44,6 +52,7 @@ }, { "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -53,8 +62,10 @@ }, { "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RFO request issued by the IRP unit to the me= sh with the intention of writing a partial cacheline to coherent memory. R= FO is a Read For Ownership command that requests ownership of the cacheline= and moves data from the mesh to IRP cache.", "UMask": "0x8", @@ -62,6 +73,7 @@ }, { "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -71,6 +83,7 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", @@ -78,6 +91,7 @@ }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -86,6 +100,7 @@ }, { "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -94,6 +109,7 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", @@ -101,14 +117,17 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.EVICTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", @@ -117,78 +136,97 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -198,8 +236,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", @@ -207,8 +247,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", "UMask": "0x40", @@ -216,8 +258,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", "UMask": "0x4", @@ -225,8 +269,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", @@ -234,8 +280,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", @@ -243,8 +291,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", @@ -252,88 +302,110 @@ }, { "BriefDescription": "P2P Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_P2P_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Requests : P2P requests from the ITC", "Unit": "IRP" }, { "BriefDescription": "P2P Occupancy", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_P2P_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P completions", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local and target = matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Message", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P reads", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : Match if remote only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if remote and target= matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Writes", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -341,8 +413,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -350,8 +424,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -359,6 +435,7 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", @@ -368,8 +445,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -377,64 +456,80 @@ }, { "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound Transaction Count : Atomic", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Atomic : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks the number of atomic transactions", "UMask": "0x10", @@ -442,8 +537,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Other", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Other : Counts t= he number of Inbound transactions from the IRP to the Uncore. This can be = filtered based on request type in addition to the source queue. Note the s= pecial filtering equation. We do OR-reduction on the request type. If the= SOURCE bit is set, then we also do AND qualification based on the source p= ortID. : Tracks the number of 'other' kinds of transactions.", "UMask": "0x20", @@ -451,8 +548,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Writes", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WRITES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Writes : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks only write requests. Each write request should have a pre= fetch, so there is no need to explicitly track these requests. For writes = that are tickled and have to retry, the counter will be incremented for eac= h retry.", "UMask": "0x2", @@ -460,6 +559,7 @@ }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -469,134 +569,170 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0x0B", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x05", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x08", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x06", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x09", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x07", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x04", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x0A", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count= as 2", "Unit": "IRP" }, { "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1B", "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0D", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0E", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0x0C", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Request Queue Occupancy : Accumulat= es the number of outstanding outbound requests from the IRP to the switch (= towards the devices). This can be used in conjunction with the allocations= event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -604,8 +740,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -613,8 +751,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -622,8 +762,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -631,8 +773,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -640,8 +784,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -649,8 +795,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -658,8 +806,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -667,8 +817,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -676,8 +828,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -685,8 +839,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -694,8 +850,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -703,8 +861,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -712,8 +872,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -721,8 +883,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -730,8 +894,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -739,8 +905,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -748,8 +916,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -757,8 +927,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -766,8 +938,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -775,8 +949,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -784,8 +960,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -793,8 +971,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -802,8 +982,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -811,8 +993,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -820,8 +1004,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -829,8 +1015,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -838,8 +1026,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -847,8 +1037,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -856,8 +1048,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -865,8 +1059,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -874,8 +1070,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -883,8 +1081,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -892,8 +1092,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -901,8 +1103,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -910,8 +1114,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -919,8 +1125,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -928,8 +1136,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -937,8 +1147,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -946,8 +1158,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -955,8 +1169,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -964,8 +1180,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -973,8 +1191,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -982,8 +1202,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -991,8 +1213,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1000,8 +1224,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1009,8 +1235,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1018,8 +1246,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1027,8 +1257,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1036,8 +1268,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1045,8 +1279,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1054,8 +1290,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1063,8 +1301,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1072,8 +1312,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1081,8 +1323,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1090,8 +1334,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1099,8 +1345,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1108,8 +1356,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1117,8 +1367,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1126,8 +1378,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1135,8 +1389,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1144,8 +1400,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1153,8 +1411,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1162,8 +1422,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1171,8 +1433,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1180,8 +1444,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1189,8 +1455,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1198,8 +1466,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1207,8 +1477,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1216,8 +1488,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1225,8 +1499,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1234,8 +1510,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1243,8 +1521,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1252,8 +1532,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1261,8 +1543,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1270,8 +1554,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1279,8 +1565,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1288,8 +1576,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1297,8 +1587,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1306,8 +1598,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1315,8 +1609,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1324,8 +1620,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1333,8 +1631,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1342,8 +1642,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1351,8 +1653,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1360,8 +1664,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1369,8 +1675,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1378,8 +1686,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1387,44 +1697,54 @@ }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", @@ -1432,29 +1752,37 @@ }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1462,8 +1790,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1471,8 +1801,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1480,8 +1812,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1489,8 +1823,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1498,8 +1834,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1507,8 +1845,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1516,8 +1856,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1525,8 +1867,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1534,8 +1878,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1543,8 +1889,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1552,8 +1900,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1561,8 +1911,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1570,8 +1922,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1579,8 +1933,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1588,8 +1944,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1597,8 +1955,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1606,8 +1966,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1615,8 +1977,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1624,8 +1988,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1633,8 +1999,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1642,8 +2010,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1651,8 +2021,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1660,8 +2032,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1669,8 +2043,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1678,8 +2054,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1687,463 +2065,581 @@ }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x704", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x201", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Chan= nels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x740", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x702", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - A= ll Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x701", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - All C= hannels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c10", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x410", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x401", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x404", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x402", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x408", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x810", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x801", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x802", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Cha= nnels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c01", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c04", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c02", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Al= l Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c08", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : MC Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : Mesh Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels"= , + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - All Channels"= , + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 0", "UMask": "0x1", @@ -2151,16 +2647,20 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI- Ch 1", "UMask": "0x4", @@ -2168,8 +2668,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 2", "UMask": "0x10", @@ -2177,8 +2679,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- All Channels", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - All Channels", "UMask": "0x15", @@ -2186,24 +2690,30 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = All Channels", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 0", "UMask": "0x1", @@ -2211,16 +2721,20 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 1", "UMask": "0x4", @@ -2228,305 +2742,383 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": ": All Channels", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -2534,8 +3126,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -2543,8 +3137,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -2552,8 +3148,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -2561,8 +3159,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -2570,8 +3170,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -2579,8 +3181,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -2588,8 +3192,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -2597,8 +3203,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -2606,197 +3214,249 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2M_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2M_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches"= , + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M2M_RxC_BL_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2804,8 +3464,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -2813,8 +3475,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -2822,8 +3486,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2831,8 +3497,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -2840,8 +3508,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -2849,8 +3519,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2858,8 +3530,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -2867,8 +3541,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -2876,8 +3552,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -2885,8 +3563,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -2894,8 +3574,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2903,8 +3585,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -2912,8 +3596,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -2921,8 +3607,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -2930,8 +3618,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2939,8 +3629,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -2948,8 +3640,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -2957,8 +3651,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -2966,8 +3662,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2975,8 +3673,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -2984,8 +3684,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -2993,8 +3695,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -3002,8 +3706,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -3011,16 +3717,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3028,8 +3738,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -3037,8 +3749,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -3046,8 +3760,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -3055,8 +3771,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -3064,8 +3782,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3073,8 +3793,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -3082,8 +3804,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -3091,8 +3815,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -3100,8 +3826,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3109,8 +3837,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -3118,8 +3848,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -3127,8 +3859,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -3136,8 +3870,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -3145,8 +3881,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3154,8 +3892,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -3163,8 +3903,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -3172,8 +3914,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -3181,8 +3925,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3190,8 +3936,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3199,8 +3947,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3208,8 +3958,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3217,8 +3969,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3226,8 +3980,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3235,8 +3991,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3244,8 +4002,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3253,8 +4013,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3262,8 +4024,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3271,8 +4035,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3280,8 +4046,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3289,8 +4057,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3298,8 +4068,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3307,8 +4079,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3316,8 +4090,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3325,8 +4101,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3334,8 +4112,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3343,8 +4123,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3352,8 +4134,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3361,8 +4145,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3370,8 +4156,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3379,8 +4167,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3388,8 +4178,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3397,8 +4189,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3406,8 +4200,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3415,8 +4211,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3424,8 +4222,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3433,8 +4233,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3442,8 +4244,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3451,8 +4255,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3460,8 +4266,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3469,8 +4277,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3478,8 +4288,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3487,8 +4299,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3496,8 +4310,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3505,8 +4321,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3514,8 +4332,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3523,8 +4343,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3532,8 +4354,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3541,8 +4365,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3550,8 +4376,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3559,8 +4387,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3568,8 +4398,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3577,573 +4409,719 @@ }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", "EventCode": "0x0d", "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x0c", "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x0b", "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_M2M_TxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : CRD Transa= ctions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : NDR Transa= ctions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.NDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AKC Credits", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Cache", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Core", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4151,8 +5129,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -4160,8 +5140,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -4169,8 +5151,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4178,8 +5162,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -4187,8 +5173,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -4196,8 +5184,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4205,8 +5195,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -4214,8 +5206,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -4223,8 +5217,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -4232,8 +5228,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -4241,8 +5239,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4250,8 +5250,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -4259,8 +5261,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -4268,8 +5272,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -4277,8 +5283,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4286,8 +5294,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -4295,8 +5305,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -4304,8 +5316,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -4313,8 +5327,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -4322,8 +5338,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4331,8 +5349,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -4340,8 +5360,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -4349,8 +5371,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -4358,8 +5382,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4367,8 +5393,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -4376,8 +5404,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4385,8 +5415,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -4394,8 +5426,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -4403,8 +5437,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4412,8 +5448,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -4421,8 +5459,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4430,8 +5470,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -4439,8 +5481,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4448,8 +5492,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -4457,8 +5503,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -4466,8 +5514,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -4475,8 +5525,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -4484,8 +5536,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4493,8 +5547,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -4502,8 +5558,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -4511,8 +5569,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -4520,8 +5580,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -4529,8 +5591,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -4538,8 +5602,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -4547,8 +5613,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -4556,8 +5624,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -4565,8 +5635,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -4574,8 +5646,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -4583,8 +5657,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -4592,8 +5668,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -4601,8 +5679,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4610,8 +5690,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -4619,8 +5701,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -4628,8 +5712,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4637,8 +5723,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -4646,8 +5734,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4655,8 +5745,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -4664,8 +5756,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -4673,8 +5767,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4682,8 +5778,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -4691,8 +5789,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -4700,8 +5800,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -4709,8 +5811,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -4718,8 +5822,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -4727,8 +5833,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -4736,8 +5844,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -4745,8 +5855,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -4754,8 +5866,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -4763,8 +5877,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -4772,8 +5888,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -4781,8 +5899,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -4790,8 +5910,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -4799,8 +5921,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -4808,8 +5932,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -4817,8 +5943,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -4826,8 +5954,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -4835,8 +5965,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -4844,8 +5976,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -4853,8 +5987,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -4862,8 +5998,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -4871,8 +6009,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -4880,8 +6020,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4889,8 +6031,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -4898,8 +6042,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -4907,8 +6053,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -4916,8 +6064,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -4925,8 +6075,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -4934,8 +6086,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4943,8 +6097,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -4952,8 +6108,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -4961,8 +6119,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4970,8 +6130,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -4979,8 +6141,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -4988,8 +6152,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -4997,8 +6163,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5006,8 +6174,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -5015,8 +6185,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5024,8 +6196,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5033,8 +6207,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -5042,8 +6218,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -5051,8 +6229,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5060,8 +6240,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -5069,8 +6251,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -5078,8 +6262,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -5087,8 +6273,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5096,8 +6284,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -5105,8 +6295,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5114,8 +6306,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -5123,8 +6317,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5132,8 +6328,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -5141,8 +6339,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -5150,8 +6350,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -5159,8 +6361,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -5168,8 +6372,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5177,8 +6383,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5186,8 +6394,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5195,8 +6405,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -5204,8 +6416,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -5213,8 +6427,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5222,8 +6438,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -5231,8 +6449,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -5240,8 +6460,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -5249,8 +6471,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5258,8 +6482,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -5267,8 +6493,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -5276,8 +6504,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -5285,8 +6515,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -5294,8 +6526,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -5303,8 +6537,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -5312,8 +6548,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -5321,8 +6559,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -5330,8 +6570,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -5339,8 +6581,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -5348,8 +6592,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -5357,8 +6603,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5366,8 +6614,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5375,8 +6625,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5384,8 +6636,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5393,8 +6647,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5402,8 +6658,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5411,8 +6669,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5420,8 +6680,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5429,8 +6691,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5438,8 +6702,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5447,8 +6713,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5456,8 +6724,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5465,8 +6735,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5474,8 +6746,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5483,8 +6757,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -5492,8 +6768,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -5501,8 +6779,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -5510,8 +6790,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -5519,8 +6801,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5528,8 +6812,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5537,8 +6823,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5546,8 +6834,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5555,254 +6845,317 @@ }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0"= , + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1"= , + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", @@ -5810,16 +7163,20 @@ }, { "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", @@ -5827,8 +7184,10 @@ }, { "BriefDescription": "Message Received : IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", "UMask": "0x4", @@ -5836,8 +7195,10 @@ }, { "BriefDescription": "Message Received : MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", "UMask": "0x2", @@ -5845,8 +7206,10 @@ }, { "BriefDescription": "Message Received : VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", "UMask": "0x1", @@ -5854,128 +7217,160 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times = an IDI Lock/SplitLock sequence was started", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", "UMask": "0x1", @@ -5983,32 +7378,40 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json b/too= ls/perf/pmu-events/arch/x86/snowridgex/uncore-io.json index de156e499f56..dff3c5a9f0d7 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_READ", "FCMask": "0x07", @@ -16,6 +17,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_WRITE", "FCMask": "0x07", @@ -31,70 +33,87 @@ }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x23", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x25", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x26", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x27", "Unit": "iio_free_running" }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -102,6 +121,7 @@ }, { "BriefDescription": "Free running counter that increments for IIO = clocktick", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", @@ -111,8 +131,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PortMask": "0xFF", @@ -121,6 +143,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -132,6 +155,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", "FCMask": "0x04", @@ -143,6 +167,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", "FCMask": "0x04", @@ -154,6 +179,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", "FCMask": "0x04", @@ -165,6 +191,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", "FCMask": "0x04", @@ -176,6 +203,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", "FCMask": "0x04", @@ -187,6 +215,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", "FCMask": "0x04", @@ -198,6 +227,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", "FCMask": "0x04", @@ -209,6 +239,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", "FCMask": "0x04", @@ -220,8 +251,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7"= , @@ -230,6 +263,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -240,6 +274,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", "FCMask": "0x04", @@ -250,6 +285,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", "FCMask": "0x04", @@ -260,6 +296,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", "FCMask": "0x04", @@ -270,6 +307,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", "FCMask": "0x04", @@ -280,6 +318,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", "FCMask": "0x04", @@ -290,6 +329,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", "FCMask": "0x04", @@ -300,6 +340,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", "FCMask": "0x04", @@ -310,6 +351,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", "FCMask": "0x04", @@ -320,8 +362,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -331,8 +375,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -342,8 +388,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -353,8 +401,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -364,8 +414,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -375,8 +427,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -386,8 +440,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -397,8 +453,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -408,8 +466,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -419,8 +479,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -430,8 +492,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -441,8 +505,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -452,8 +518,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -463,8 +531,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -474,8 +544,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -485,8 +557,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -496,8 +570,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -507,8 +583,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -518,8 +596,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -529,8 +609,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -540,8 +622,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -551,8 +635,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -562,8 +648,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -573,8 +661,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -584,8 +674,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -595,8 +687,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -606,8 +700,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -617,8 +713,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -628,8 +726,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -639,8 +739,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -650,8 +752,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -661,8 +765,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -672,8 +778,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -683,8 +791,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -694,8 +804,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -705,8 +817,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -716,8 +830,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -727,8 +843,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -738,8 +856,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -749,8 +869,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -760,8 +882,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -771,8 +895,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -782,6 +908,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -793,6 +920,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -804,6 +932,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -815,6 +944,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -826,6 +956,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -837,6 +968,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -848,6 +980,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -859,6 +992,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -870,8 +1004,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -881,8 +1017,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -892,6 +1030,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -903,6 +1042,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -914,6 +1054,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -925,6 +1066,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -936,6 +1078,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -947,6 +1090,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -958,6 +1102,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -969,6 +1114,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -980,8 +1126,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -991,8 +1139,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1002,8 +1152,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1013,8 +1165,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1024,8 +1178,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1035,8 +1191,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1046,8 +1204,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1057,8 +1217,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1068,8 +1230,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1079,8 +1243,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1090,8 +1256,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1101,8 +1269,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1112,8 +1282,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1123,8 +1295,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1134,8 +1308,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1145,8 +1321,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1156,8 +1334,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1167,8 +1347,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1178,8 +1360,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1189,8 +1373,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1200,8 +1386,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1211,8 +1399,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1222,8 +1412,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1233,8 +1425,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1244,8 +1438,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1255,8 +1451,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1266,8 +1464,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1277,8 +1477,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1288,8 +1490,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1299,8 +1503,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1310,8 +1516,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1321,8 +1529,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1332,6 +1542,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -1343,6 +1554,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -1354,6 +1566,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -1365,6 +1578,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -1376,6 +1590,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -1387,6 +1602,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -1398,6 +1614,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -1409,6 +1626,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -1420,8 +1638,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1431,8 +1651,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1442,6 +1664,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 0"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1453,6 +1676,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 1"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1464,6 +1688,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 2"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1475,6 +1700,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 3"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1486,6 +1712,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1497,6 +1724,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1508,6 +1736,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1519,6 +1748,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1530,8 +1760,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1541,8 +1773,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1552,6 +1786,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 0"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1563,6 +1798,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 1"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1574,6 +1810,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 2"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1585,6 +1822,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 3"= , + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1596,6 +1834,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1607,6 +1846,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1618,6 +1858,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1629,6 +1870,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1640,8 +1882,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1651,8 +1895,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1662,8 +1908,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1673,8 +1921,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1684,8 +1934,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1695,8 +1947,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1706,8 +1960,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1717,8 +1973,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1728,8 +1986,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1739,8 +1999,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1750,8 +2012,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1761,8 +2025,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1772,8 +2038,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1783,8 +2051,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1794,8 +2064,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1805,8 +2077,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1816,8 +2090,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1827,8 +2103,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1838,8 +2116,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1849,8 +2129,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1860,8 +2142,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1871,8 +2155,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1882,8 +2168,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1893,8 +2181,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1904,8 +2194,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1915,8 +2207,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1926,8 +2220,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1937,8 +2233,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1948,8 +2246,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1959,8 +2259,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1970,8 +2272,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1981,8 +2285,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1992,8 +2298,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2003,8 +2311,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2014,8 +2324,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2025,8 +2337,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Writing line"= , + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2036,8 +2350,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2047,8 +2363,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2058,8 +2376,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2069,8 +2389,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2080,8 +2402,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2091,8 +2415,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2102,8 +2428,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", "UMask": "0x10", @@ -2111,8 +2439,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", "UMask": "0x8", @@ -2120,8 +2450,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", "UMask": "0x4", @@ -2129,8 +2461,10 @@ }, { "BriefDescription": ": IOTLB lookups all", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups all : Some transactions have= to look up IOTLB multiple times. Counts every time a request looks up IOT= LB.", "UMask": "0x2", @@ -2138,8 +2472,10 @@ }, { "BriefDescription": ": Context cache hits", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", "UMask": "0x80", @@ -2147,8 +2483,10 @@ }, { "BriefDescription": ": Context cache lookups", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", "UMask": "0x40", @@ -2156,8 +2494,10 @@ }, { "BriefDescription": ": IOTLB lookups first", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", "UMask": "0x1", @@ -2165,8 +2505,10 @@ }, { "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a = transaction misses IOTLB, it does a page walk to look up memory and bring i= n the relevant page translation. Counts when this page translation is writt= en to IOTLB.", "UMask": "0x20", @@ -2174,8 +2516,10 @@ }, { "BriefDescription": ": Cycles PWT full", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU = has reached its maximum limit for outstanding page walks.", "UMask": "0x80", @@ -2183,8 +2527,10 @@ }, { "BriefDescription": ": IOMMU memory access", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", "UMask": "0x40", @@ -2192,8 +2538,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -2201,8 +2549,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -2210,8 +2560,10 @@ }, { "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", "UMask": "0x2", @@ -2219,8 +2571,10 @@ }, { "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", "UMask": "0x10", @@ -2228,8 +2582,10 @@ }, { "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", "UMask": "0x20", @@ -2237,8 +2593,10 @@ }, { "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", "UMask": "0x1", @@ -2246,8 +2604,10 @@ }, { "BriefDescription": ": Interrupt Entry cache hit", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache hit : Counts each ti= me a transaction's first look up hits the IEC.", "UMask": "0x80", @@ -2255,8 +2615,10 @@ }, { "BriefDescription": ": Interrupt Entry cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache lookup : Counts the = number of transaction looks up that interrupt remapping cache.", "UMask": "0x40", @@ -2264,8 +2626,10 @@ }, { "BriefDescription": ": Device-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Device-selective Context cache invalidatio= n cycles : Counts number of Device selective context cache invalidation eve= nts", "UMask": "0x20", @@ -2273,8 +2637,10 @@ }, { "BriefDescription": ": Domain-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective Context cache invalidatio= n cycles : Counts number of Domain selective context cache invalidation eve= nts", "UMask": "0x10", @@ -2282,8 +2648,10 @@ }, { "BriefDescription": ": Context cache global invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache global invalidation cycles := Counts number of Context Cache global invalidation events", "UMask": "0x8", @@ -2291,8 +2659,10 @@ }, { "BriefDescription": ": Domain-selective IOTLB invalidation cycles"= , + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective IOTLB invalidation cycles= : Counts number of Domain selective invalidation events", "UMask": "0x2", @@ -2300,8 +2670,10 @@ }, { "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", "UMask": "0x1", @@ -2309,8 +2681,10 @@ }, { "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Page-selective IOTLB invalidation cycles := Counts number of Page-selective within Domain Invalidation events", "UMask": "0x4", @@ -2318,8 +2692,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", "UMask": "0x1", @@ -2327,8 +2703,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x8", @@ -2336,8 +2714,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x4", @@ -2345,8 +2725,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", "UMask": "0x2", @@ -2354,8 +2736,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x10", @@ -2363,8 +2747,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x20", @@ -2372,8 +2758,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", "UMask": "0x1", @@ -2381,8 +2769,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x8", @@ -2390,8 +2780,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x4", @@ -2399,8 +2791,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", "UMask": "0x2", @@ -2408,8 +2802,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x10", @@ -2417,8 +2813,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x20", @@ -2426,15 +2824,19 @@ }, { "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_IIO_NOTHING", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Occupancy of outbound request queue : To devi= ce", + "Counter": "2,3", "EventCode": "0xC5", "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2444,8 +2846,10 @@ }, { "BriefDescription": ": Passing data to be written", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2455,8 +2859,10 @@ }, { "BriefDescription": ": Issuing final read or write of line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2465,8 +2871,10 @@ }, { "BriefDescription": ": Processing response from IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2475,8 +2883,10 @@ }, { "BriefDescription": ": Issuing to IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2485,8 +2895,10 @@ }, { "BriefDescription": ": Request Ownership", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2496,8 +2908,10 @@ }, { "BriefDescription": ": Writing line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2507,8 +2921,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = From ITC", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2518,8 +2934,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = Completion allocations", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2528,8 +2946,10 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = Drop request", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2539,6 +2959,7 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", @@ -2550,8 +2971,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2560,8 +2983,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2570,8 +2995,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2580,8 +3007,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2590,8 +3019,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2600,8 +3031,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : MsgB"= , + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2610,8 +3043,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2620,8 +3055,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Ubox"= , + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2630,15 +3067,19 @@ }, { "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2648,8 +3089,10 @@ }, { "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2659,16 +3102,20 @@ }, { "BriefDescription": "PWT occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", "Unit": "IIO" }, { "BriefDescription": "PCIe Request - cacheline complete : Passing d= ata to be written", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2678,8 +3125,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Issuing f= inal read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2689,8 +3138,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Request O= wnership", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2700,8 +3151,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Writing l= ine", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2711,8 +3164,10 @@ }, { "BriefDescription": "PCIe Request complete : Passing data to be wr= itten", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2722,8 +3177,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing final read or= write of line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2733,8 +3190,10 @@ }, { "BriefDescription": "PCIe Request complete : Processing response f= rom IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2744,8 +3203,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2755,8 +3216,10 @@ }, { "BriefDescription": "PCIe Request complete : Request Ownership", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2766,8 +3229,10 @@ }, { "BriefDescription": "PCIe Request complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2777,8 +3242,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2788,8 +3255,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2799,8 +3268,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2810,8 +3281,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2821,16 +3294,20 @@ }, { "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_IIO_SYMBOL_TIMES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Symbol Times on Link : Gen1 - increment once= every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1n= S", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2840,8 +3317,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2851,8 +3330,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2862,8 +3343,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2873,8 +3356,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2884,8 +3369,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -2895,8 +3382,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -2906,8 +3395,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -2917,8 +3408,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -2928,8 +3421,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -2939,8 +3434,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2950,8 +3447,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2961,8 +3460,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2972,8 +3473,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2983,8 +3486,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2994,8 +3499,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3005,8 +3512,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3016,8 +3525,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3027,8 +3538,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3038,8 +3551,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3049,8 +3564,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3060,8 +3577,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3071,8 +3590,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3082,8 +3603,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3093,8 +3616,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3104,8 +3629,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3115,8 +3642,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3126,8 +3655,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3137,8 +3668,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3148,8 +3681,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3159,8 +3694,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3170,8 +3707,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3181,8 +3720,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3192,8 +3733,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3203,8 +3746,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3214,8 +3759,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3225,8 +3772,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3236,8 +3785,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3247,8 +3798,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3258,8 +3811,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3269,8 +3824,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3280,8 +3837,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3291,6 +3850,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3302,6 +3862,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3313,6 +3874,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3324,6 +3886,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3335,6 +3898,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3346,6 +3910,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -3357,6 +3922,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -3368,6 +3934,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -3379,8 +3946,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3390,8 +3959,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3401,6 +3972,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3412,6 +3984,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3423,6 +3996,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3434,6 +4008,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3445,6 +4020,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -3456,6 +4032,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -3467,6 +4044,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -3478,6 +4056,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -3489,8 +4068,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3500,8 +4081,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3511,8 +4094,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3522,8 +4107,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3533,8 +4120,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3544,8 +4133,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3555,8 +4146,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3566,8 +4159,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3577,8 +4172,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3588,8 +4185,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3599,8 +4198,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3610,8 +4211,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3621,8 +4224,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3632,8 +4237,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3643,8 +4250,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3654,8 +4263,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3665,8 +4276,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3676,8 +4289,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3687,8 +4302,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3698,8 +4315,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3709,8 +4328,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3720,8 +4341,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3731,8 +4354,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3742,8 +4367,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3753,8 +4380,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3764,8 +4393,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3775,8 +4406,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3786,8 +4419,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3797,8 +4432,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3808,8 +4445,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3819,8 +4458,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3830,6 +4471,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -3841,6 +4483,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -3852,6 +4495,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -3863,6 +4507,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -3874,6 +4519,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -3885,6 +4531,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -3896,6 +4543,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -3907,6 +4555,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -3918,8 +4567,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3929,8 +4580,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3940,6 +4593,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3951,6 +4605,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3962,6 +4617,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3973,6 +4629,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3984,6 +4641,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3995,6 +4653,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -4006,6 +4665,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -4017,6 +4677,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -4028,8 +4689,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4039,8 +4702,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4050,6 +4715,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -4061,6 +4727,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -4072,6 +4739,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -4083,6 +4751,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -4094,6 +4763,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -4105,6 +4775,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -4116,6 +4787,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -4127,6 +4799,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -4138,8 +4811,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4149,8 +4824,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4160,8 +4837,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4171,8 +4850,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4182,8 +4863,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4193,8 +4876,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4204,8 +4889,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4215,8 +4902,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4226,8 +4915,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4237,8 +4928,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4248,8 +4941,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4259,8 +4954,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4270,8 +4967,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4281,8 +4980,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4292,8 +4993,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4303,8 +5006,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4314,8 +5019,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4325,8 +5032,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4336,8 +5045,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4347,8 +5058,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4358,8 +5071,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4369,8 +5084,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4380,8 +5097,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4391,8 +5110,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4402,8 +5123,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4413,8 +5136,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4424,8 +5149,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4435,8 +5162,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4446,8 +5175,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4457,8 +5188,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4468,8 +5201,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4477,8 +5212,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4486,8 +5223,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4495,8 +5234,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4504,8 +5245,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4513,8 +5256,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4522,8 +5267,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4531,8 +5278,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4540,8 +5289,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4549,8 +5300,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4558,8 +5311,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4567,8 +5322,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4576,8 +5333,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4585,8 +5344,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4594,8 +5355,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4603,8 +5366,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4612,8 +5377,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4621,8 +5388,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4630,8 +5399,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4639,8 +5410,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4648,8 +5421,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4657,8 +5432,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4666,8 +5443,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4675,8 +5454,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4684,8 +5465,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4693,8 +5476,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4702,8 +5487,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4711,8 +5498,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4720,8 +5509,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4729,8 +5520,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4738,8 +5531,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4747,8 +5542,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4756,8 +5553,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4765,8 +5564,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4774,8 +5575,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4783,8 +5586,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4792,8 +5597,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4801,8 +5608,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4810,8 +5619,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4819,8 +5630,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4828,8 +5641,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4837,8 +5652,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4846,8 +5663,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4855,8 +5674,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4864,8 +5685,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4873,8 +5696,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4882,8 +5707,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4891,8 +5718,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4900,8 +5729,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4909,8 +5740,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4918,8 +5751,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4927,8 +5762,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4936,8 +5773,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4945,8 +5784,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4954,8 +5795,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4963,8 +5806,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4972,8 +5817,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4981,8 +5828,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4990,8 +5839,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4999,8 +5850,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -5008,8 +5861,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -5017,8 +5872,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -5026,8 +5883,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5035,8 +5894,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5044,8 +5905,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5053,8 +5916,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5062,8 +5927,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5071,8 +5938,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5080,8 +5949,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -5089,8 +5960,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -5098,8 +5971,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -5107,8 +5982,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -5116,8 +5993,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -5125,8 +6004,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -5134,8 +6015,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -5143,8 +6026,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5152,8 +6037,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5161,8 +6048,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5170,8 +6059,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5179,8 +6070,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -5188,8 +6081,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -5197,8 +6092,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -5206,8 +6103,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -5215,8 +6114,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -5224,8 +6125,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5233,8 +6136,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5242,8 +6147,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5251,8 +6158,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5260,6 +6169,7 @@ }, { "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", @@ -5267,6 +6177,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", @@ -5274,8 +6185,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -5283,8 +6196,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -5292,8 +6207,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -5301,8 +6218,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -5310,8 +6229,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -5319,8 +6240,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -5328,8 +6251,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -5337,8 +6262,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -5346,8 +6273,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5355,8 +6284,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5364,8 +6295,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5373,8 +6306,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5382,8 +6317,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5391,8 +6328,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5400,8 +6339,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5409,8 +6350,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5418,8 +6361,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5427,8 +6372,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5436,8 +6383,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5445,8 +6394,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5454,8 +6405,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5463,8 +6416,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5472,8 +6427,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5481,8 +6438,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5490,8 +6449,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -5499,8 +6460,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -5508,8 +6471,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x1", @@ -5517,8 +6482,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x2", @@ -5526,8 +6493,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x4", @@ -5535,8 +6504,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x8", @@ -5544,8 +6515,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", @@ -5553,8 +6526,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", @@ -5562,8 +6537,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", "UMask": "0x8", @@ -5571,8 +6548,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", "UMask": "0x10", @@ -5580,8 +6559,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", "UMask": "0x20", @@ -5589,8 +6570,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x1", @@ -5598,8 +6581,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x2", @@ -5607,8 +6592,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x4", @@ -5616,8 +6603,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x8", @@ -5625,8 +6614,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", "UMask": "0x10", @@ -5634,8 +6625,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", "UMask": "0x20", @@ -5643,648 +6636,810 @@ }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -6292,8 +7447,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -6301,8 +7458,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -6310,8 +7469,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -6319,8 +7480,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -6328,8 +7491,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -6337,8 +7502,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -6346,8 +7513,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -6355,8 +7524,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -6364,95 +7535,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2P_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2PCIe" }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x80", @@ -6460,8 +7655,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x1", @@ -6469,8 +7666,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x2", @@ -6478,8 +7677,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x4", @@ -6487,8 +7688,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x20", @@ -6496,8 +7699,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x40", @@ -6505,8 +7710,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x80", @@ -6514,8 +7721,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x1", @@ -6523,8 +7732,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x2", @@ -6532,8 +7743,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x4", @@ -6541,8 +7754,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x20", @@ -6550,8 +7765,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x40", @@ -6559,8 +7776,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6568,8 +7787,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -6577,8 +7798,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -6586,8 +7809,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6595,8 +7820,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -6604,8 +7831,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -6613,8 +7842,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6622,8 +7853,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -6631,8 +7864,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -6640,8 +7875,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -6649,8 +7886,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -6658,8 +7897,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6667,8 +7908,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -6676,8 +7919,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -6685,8 +7930,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -6694,8 +7941,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6703,8 +7952,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -6712,8 +7963,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -6721,8 +7974,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -6730,8 +7985,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6739,8 +7996,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -6748,8 +8007,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -6757,8 +8018,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -6766,8 +8029,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -6775,16 +8040,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6792,8 +8061,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -6801,8 +8072,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -6810,8 +8083,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -6819,8 +8094,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -6828,8 +8105,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6837,8 +8116,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -6846,8 +8127,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -6855,8 +8138,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -6864,8 +8149,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6873,8 +8160,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -6882,8 +8171,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -6891,8 +8182,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -6900,8 +8193,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -6909,8 +8204,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6918,8 +8215,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited"= , + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -6927,8 +8226,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -6936,8 +8237,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -6945,8 +8248,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -6954,8 +8259,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -6963,8 +8270,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -6972,8 +8281,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -6981,8 +8292,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -6990,8 +8303,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -6999,8 +8314,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7008,8 +8325,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7017,8 +8336,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7026,8 +8347,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7035,8 +8358,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7044,8 +8369,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7053,8 +8380,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7062,8 +8391,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7071,8 +8402,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7080,8 +8413,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7089,8 +8424,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7098,8 +8435,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7107,8 +8446,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7116,8 +8457,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7125,8 +8468,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7134,8 +8479,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7143,8 +8490,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7152,8 +8501,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7161,8 +8512,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7170,8 +8523,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7179,8 +8534,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7188,8 +8545,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7197,8 +8556,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7206,8 +8567,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7215,8 +8578,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7224,8 +8589,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7233,8 +8600,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7242,8 +8611,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7251,8 +8622,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7260,8 +8633,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7269,8 +8644,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7278,8 +8655,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7287,8 +8666,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7296,8 +8677,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7305,8 +8688,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7314,8 +8699,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7323,8 +8710,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7332,8 +8721,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7341,16 +8732,20 @@ }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x1", @@ -7358,8 +8753,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x10", @@ -7367,8 +8764,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x2", @@ -7376,8 +8775,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x20", @@ -7385,8 +8786,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x4", @@ -7394,8 +8797,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x40", @@ -7403,8 +8808,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x1", @@ -7412,8 +8819,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x10", @@ -7421,8 +8830,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x2", @@ -7430,8 +8841,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x20", @@ -7439,8 +8852,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x4", @@ -7448,8 +8863,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x40", @@ -7457,8 +8874,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x1", @@ -7466,8 +8885,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x10", @@ -7475,8 +8896,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x8", @@ -7484,8 +8907,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x80", @@ -7493,8 +8918,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x4", @@ -7502,8 +8929,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x40", @@ -7511,8 +8940,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7520,8 +8951,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -7529,8 +8962,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -7538,8 +8973,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7547,8 +8984,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -7556,8 +8995,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -7565,8 +9006,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7574,8 +9017,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -7583,8 +9028,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -7592,8 +9039,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -7601,8 +9050,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -7610,8 +9061,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7619,8 +9072,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -7628,8 +9083,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited"= , + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -7637,8 +9094,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -7646,8 +9105,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7655,8 +9116,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -7664,8 +9127,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -7673,8 +9138,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -7682,8 +9149,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -7691,8 +9160,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7700,8 +9171,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -7709,8 +9182,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -7718,8 +9193,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -7727,8 +9204,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7736,8 +9215,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -7745,8 +9226,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -7754,8 +9237,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -7763,8 +9248,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -7772,8 +9259,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7781,8 +9270,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -7790,8 +9281,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -7799,8 +9292,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -7808,8 +9303,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7817,8 +9314,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -7826,8 +9325,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -7835,8 +9336,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -7844,8 +9347,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -7853,8 +9358,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7862,8 +9369,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -7871,8 +9380,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -7880,8 +9391,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -7889,8 +9402,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -7898,8 +9413,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -7907,8 +9424,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -7916,8 +9435,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -7925,8 +9446,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -7934,8 +9457,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -7943,8 +9468,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -7952,8 +9479,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -7961,8 +9490,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -7970,8 +9501,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7979,8 +9512,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -7988,8 +9523,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -7997,8 +9534,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8006,8 +9545,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -8015,8 +9556,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8024,8 +9567,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -8033,8 +9578,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -8042,8 +9589,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8051,8 +9600,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -8060,8 +9611,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -8069,8 +9622,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -8078,8 +9633,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -8087,8 +9644,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -8096,8 +9655,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -8105,8 +9666,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -8114,8 +9677,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -8123,8 +9688,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -8132,8 +9699,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -8141,8 +9710,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -8150,8 +9721,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -8159,8 +9732,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -8168,8 +9743,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -8177,8 +9754,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -8186,8 +9765,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -8195,8 +9776,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -8204,8 +9787,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -8213,8 +9798,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -8222,8 +9809,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -8231,8 +9820,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8240,8 +9831,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -8249,8 +9842,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8258,8 +9853,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8267,8 +9864,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8276,8 +9875,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8285,8 +9886,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -8294,8 +9897,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8303,8 +9908,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8312,8 +9919,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -8321,8 +9930,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -8330,8 +9941,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8339,8 +9952,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8348,8 +9963,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8357,8 +9974,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8366,8 +9985,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -8375,8 +9996,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -8384,8 +10007,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8393,8 +10018,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8402,8 +10029,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -8411,8 +10040,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -8420,8 +10051,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8429,8 +10062,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -8438,8 +10073,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -8447,8 +10084,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -8456,8 +10095,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8465,8 +10106,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -8474,8 +10117,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8483,8 +10128,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -8492,8 +10139,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8501,8 +10150,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -8510,8 +10161,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -8519,8 +10172,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -8528,8 +10183,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -8537,8 +10194,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8546,8 +10205,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8555,8 +10216,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8564,8 +10227,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -8573,8 +10238,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -8582,8 +10249,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8591,8 +10260,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -8600,8 +10271,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -8609,8 +10282,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -8618,8 +10293,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8627,8 +10304,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -8636,8 +10315,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -8645,8 +10326,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -8654,8 +10337,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -8663,8 +10348,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -8672,8 +10359,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -8681,8 +10370,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -8690,8 +10381,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -8699,8 +10392,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -8708,8 +10403,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -8717,8 +10414,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -8726,8 +10425,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8735,8 +10436,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8744,8 +10447,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8753,8 +10458,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8762,8 +10469,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8771,8 +10480,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8780,8 +10491,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8789,8 +10502,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8798,8 +10513,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8807,8 +10524,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8816,8 +10535,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8825,8 +10546,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8834,8 +10557,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8843,8 +10568,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8852,8 +10579,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -8861,8 +10590,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -8870,8 +10601,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -8879,8 +10612,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -8888,8 +10623,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8897,8 +10634,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8906,8 +10645,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8915,8 +10656,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json index b80911d498dd..2f6907cba7f6 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,6 +23,7 @@ }, { "BriefDescription": "DRAM Activate Count : All Activates", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -30,8 +33,10 @@ }, { "BriefDescription": "DRAM Activate Count : Activate due to Bypass"= , + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Activate Count : Activate due to Bypass= : Counts the number of DRAM Activate commands sent on this channel. Activ= ate commands are issued to open up a page on the DRAM devices so that it ca= n be read or written to with a CAS. One can calculate the number of Page M= isses by subtracting the number of Page Miss precharges from the number of = Activates.", "UMask": "0x8", @@ -39,6 +44,7 @@ }, { "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -57,8 +64,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CA= S commands w/auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total= number or DRAM Read CAS commands issued on this channel. This includes bo= th regular RD CAS commands as well as those with explicit Precharge. AutoP= re is only used in systems that are using closed page policy. We do not fi= lter based on major mode, as RD_CAS is not issued during WMM (with the exce= ption of underfills).", "UMask": "0x2", @@ -66,8 +75,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0x8", @@ -75,8 +86,10 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of DRAM Read CAS com= mands issued on this channel. This includes both regular RD CAS commands a= s well as those with implicit Precharge. We do not filter based on major = mode, as RD_CAS is not issued during WMM (with the exception of underfills)= .", "UMask": "0x1", @@ -84,8 +97,10 @@ }, { "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total of DRAM Read CAS commands i= ssued due to an underfill", "UMask": "0x4", @@ -93,6 +108,7 @@ }, { "BriefDescription": "All DRAM write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -102,8 +118,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x10", @@ -111,8 +129,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/ auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x20", @@ -120,6 +140,7 @@ }, { "BriefDescription": "Memory controller clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Clockticks of the integrated memory controll= er (IMC)", @@ -127,22 +148,27 @@ }, { "BriefDescription": "Free running counter that increments for the = Memory Controller", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "imc_free_running" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -152,6 +178,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", "PerPkg": "1", @@ -161,6 +188,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -170,6 +198,7 @@ }, { "BriefDescription": "Half clockticks for IMC", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", @@ -177,39 +206,49 @@ }, { "BriefDescription": "UNC_M_PARITY_ERRORS", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M_PARITY_ERRORS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.TOTAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", + "Experimental": "1", "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100"= , "MetricName": "power_channel_ppd", "PerPkg": "1", @@ -218,8 +257,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x1", @@ -227,8 +268,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x2", @@ -236,8 +279,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x4", @@ -245,8 +290,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x8", @@ -254,8 +301,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -263,8 +312,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -272,8 +323,10 @@ }, { "BriefDescription": "Cycles Memory is in self refresh power mode", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", + "Experimental": "1", "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", "MetricName": "power_self_refresh", "PerPkg": "1", @@ -282,8 +335,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -291,8 +346,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -300,6 +357,7 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -309,8 +367,10 @@ }, { "BriefDescription": "Pre-charges due to page misses", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = page miss : Counts the number of DRAM Precharge commands sent on this chann= el. : Pages Misses are due to precharges from bank scheduler (rd/wr request= s)", "UMask": "0xc", @@ -318,6 +378,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -327,6 +388,7 @@ }, { "BriefDescription": "Pre-charge for reads", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -336,6 +398,7 @@ }, { "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -345,52 +408,66 @@ }, { "BriefDescription": "Read Data Buffer Full", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NOT_EMPTY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x1", @@ -398,8 +475,10 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x2", @@ -407,6 +486,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", @@ -416,6 +496,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", @@ -425,6 +506,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -433,6 +515,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -441,24 +524,30 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x1", @@ -466,8 +555,10 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x2", @@ -475,6 +566,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", @@ -484,6 +576,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", @@ -493,6 +586,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -501,6 +595,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -509,8 +604,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -518,8 +615,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -527,8 +626,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -536,8 +637,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json index dcf268467db9..1d59c9b65b3f 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json @@ -1,153 +1,192 @@ [ { "BriefDescription": "Clockticks of the power control unit (PCU)", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C3 : Counts the = number of cycles when the package was in C3. This event can be used in con= junction with edge detect to count C3 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State : C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C0 and C1 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0x40", @@ -155,8 +194,10 @@ }, { "BriefDescription": "Number of cores in C-State : C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C3 : This is an= occupancy event that tracks the number of cores that are in the chosen C-S= tate. It can be used by itself to get the average number of cores in that = C-state with thresholding to generate histograms, or with other PCU events = and occupancy triggering to capture other details.", "UMask": "0x80", @@ -164,8 +205,10 @@ }, { "BriefDescription": "Number of cores in C-State : C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C6 and C7 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0xc0", @@ -173,32 +216,40 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json index cabe29e70e79..f9a6caed8776 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of page walks due to loads = that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccount for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for demand loads every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for demand loads every cycle. A page walk i= s outstanding from start till PMH becomes idle again (ready to serve next w= alk). Includes EPT-walk intervals.", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Counts the number of page walks due to stores= that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", @@ -85,6 +96,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -101,6 +114,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_HIT", "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", @@ -117,6 +132,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_MISS", "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", @@ -125,6 +141,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_HIT", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", @@ -133,6 +150,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_MISS", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", @@ -149,6 +168,7 @@ }, { "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.FILLS", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -164,6 +185,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB."= , + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -171,6 +193,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -179,6 +202,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", @@ -187,6 +211,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -195,6 +220,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -203,6 +229,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for instruction fetches every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", @@ -211,6 +238,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked due to a first level TLB miss.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DTLB_MISS", "PEBS": "1", @@ -219,6 +247,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= missed in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", @@ -228,6 +257,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the second Level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Counts the number of store uops retired that = miss in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", --=20 2.45.2.627.g7a2c4fd464-goog