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Date: Sat, 15 Jun 2024 20:16:11 +0100
From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Conor Dooley" <conor@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>, "Lee Jones" <lee@kernel.org>,
 "Krzysztof Kozlowski" <krzk+dt@kernel.org>,
 "Conor Dooley" <conor+dt@kernel.org>,
 "paulburton@kernel.org" <paulburton@kernel.org>,
 "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
 "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Subject: Re: [PATCH v2 7/8] du-bindings: mips: cpu: Add img,mips compatible
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=E5=9C=A82024=E5=B9=B46=E6=9C=8815=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=E5=
=8D=881:28=EF=BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A
> On Thu, Jun 13, 2024 at 08:40:18PM +0100, Jiaxun Yang wrote:
>>=20
>>=20
>> =E5=9C=A82024=E5=B9=B46=E6=9C=8813=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=
=E5=8D=887:59=EF=BC=8CRob Herring=E5=86=99=E9=81=93=EF=BC=9A
>> > On Wed, Jun 12, 2024 at 05:59:24PM +0100, Jiaxun Yang wrote:
>> >>=20
>> >>=20
>> >> =E5=9C=A82024=E5=B9=B46=E6=9C=8812=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=
=8B=E5=8D=885:39=EF=BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A
>> >> > On Wed, Jun 12, 2024 at 12:56:26PM +0100, Jiaxun Yang wrote:
>> >> >> This compatible is used by boston.dts.
>> >> >>=20
>> >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> >> >> ---
>> >> >> note: This is a wildcard compatible for all MIPS CPUs,
>> >> >>       I think we should use something like "riscv" for riscv.
>> >> >
>> >> > riscv systems, other than simulators etc are not meant to use the
>> >> > "riscv" compatible. All of the real CPUs use "vendor,cpu", "risc=
v".
>> >> > I'd suggest you add specific compatibles for your CPUs.
>> >>=20
>> >> Boston can be combined with many different CPUs, thus we need to h=
ave
>> >> such compatibles.
>> >
>> > Then you'll need different DTs. Different h/w, different DT.
>>=20
>> The board have 9 CPU types in total, with hundreds of different possi=
ble
>> CPU topologies. Maintaining separate DT for them seems impossible in =
kernel.
>
> But you could definitely add 9 different compatibles for each of these
> different CPUs.

They are already in current bindings, but we need a default one to fill
in kernel dts.

>
>> We can potentially patch this in bootloader, but for existing firmwar=
e it's
>> being doing like this for years. I can see for RISC-V QEMU generated =
DTB is
>> using a single "riscv" compatible and I do think it's a similar probl=
em.
>
> That "riscv" compatible is only supposed to be used for
> simulators/software models. Real CPUs are not meant to use it. AFAICT,
> your boston is a real platform, even if the CPUs are implemented on an
> FPGA they should still have one. If you take the OpenC906 RISC-V CPU a=
nd
> put it on an FPGA, you're still meant to put "thead,c906" in your DT.
>

And sadly, boston is also the platform used by MIPS internal emulators :=
-(

Thanks
- Jiaxun
>
> =E9=99=84=E4=BB=B6:
> * signature.asc

--=20
- Jiaxun