Message-ID: <47ACDE09.7020805@linux.intel.com>
Date: Fri, 08 Feb 2008 14:56:09 -0800
From: Arjan van de Ven <arjan@linux.intel.com>
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To: Nick Piggin <npiggin@suse.de>
CC: David Miller <davem@davemloft.net>, torvalds@linux-foundation.org,
       mingo@elte.hu, jens.axboe@oracle.com, linux-kernel@vger.kernel.org,
       Alan.Brunelle@hp.com, dgc@sgi.com, akpm@linux-foundation.org,
       vegard.nossum@gmail.com, penberg@gmail.com
Subject: Re: [patch] block layer: kmemcheck fixes
References: <20080207103136.GG15220@kernel.dk> <20080207104901.GF16735@elte.hu> <alpine.LFD.1.00.0802070940230.2883@woody.linux-foundation.org> <20080207.172246.31415231.davem@davemloft.net> <47AC7093.1070003@linux.intel.com> <20080208224427.GC4952@wotan.suse.de>
In-Reply-To: <20080208224427.GC4952@wotan.suse.de>
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Nick Piggin wrote:
>>> Maybe cpus these days have so much store bandwith that doing
>>> things like the above is OK, but I doubt it :-)
>> on modern x86 cpus the memset may even be faster if the memory isn't in 
>> cache;
>> the "explicit" method ends up doing Write Allocate on the cache lines
>> (so read them from memory) even though they then end up being written 
>> entirely.
>> With memset the CPU is told that the entire range is set to a new value, and
>> the WA can be avoided for the whole-cachelines in the range.
> 
> Don't you have write combining store buffers? Or is it still speculatively
> issuing the reads even before the whole cacheline is combined?

x86 memory order model doesn't allow that quite; and you need a "series" of at least 64 bytes
without any other memory accesses in between even if it would....
not happening in practice.
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