From: Andi Kleen <ak@suse.de>
Organization: SUSE Linux Products GmbH, Nuernberg, GF: Markus Rex, HRB 16746 (AG Nuernberg)
To: Arjan van de Ven <arjan@infradead.org>
Subject: Re: [PATCH] [7/8] CPA: Don't flush caches on CPUs that support self-snoop
Date: Mon, 11 Feb 2008 16:12:56 +0100
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On Monday 11 February 2008 16:04:30 Arjan van de Ven wrote:
> On Mon, 11 Feb 2008 10:50:22 +0100 (CET)
> Andi Kleen <ak@suse.de> wrote:
> 
> > 
> > [2.6.25 candidate I believe]
> > 
> > The specification of SS in the public manuals is a little unclear,
> > but I got confirmation from Intel that SS implies that there is no
> > cache flush needed on caching attribute changes.
> 
> I'm hearing slightly different information, but am still chasing this one.

10.12.8 in the ia32 manual volume 3a says:

"
When remapping a page that was previously mapped as a cacheable memory type to
a WC page, an operating system can avoid this type of aliasing by doing the
following:
...

3. Create a new mapping to the same physical address with a new memory type, for
   instance, WC.
4. Flush the caches on all processors that may have used the mapping previously.
   Note on processors that support self-snooping, CPUID feature flag bit 27, this
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
   step is unnecessary.
   ^^^^^^^^^^^^^^^^^^^^
"

That is exactly the situation in pageattr.c. You're saying the manual is wrong
here?

> It might be better to delay this one to .26 ;-(
> (I would very much like to avoid the cache flush but... it really HAS to be safe)

Unless there are known errata (i'm not aware of any) it is safe according to the manual.

-Andi

 
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