Date: Mon, 18 Feb 2008 15:31:58 +0100
From: Haavard Skinnemoen <hskinnemoen@atmel.com>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: david-b@pacbell.net, spi-devel-general@lists.sourceforge.net,
       linux-kernel@vger.kernel.org
Subject: Re: atmel_spi clock polarity
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On Mon, 18 Feb 2008 23:12:43 +0900 (JST)
Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:

> T0-T1 was relatively longer then T1-T2.  I suppose T1 is not the
> point of updating MR register, but the point of starting DMA transfer.

Aw. I see.

> Anyway, I will try your patch in a few days.

Ok, thanks. If it works, that would be great, but given your
description above I'm not sure if I dare hope for it.

Hmm...I suppose we could just use CSR0 for all transfers and not
bother updating MR. That might actually be cheaper than doing it
"the right way"...and allow us to support an arbitrary number of
chipselects instead of just four.

But I guess the AT91RM9200 won't be too happy about that...

Haavard
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