Date: Mon, 18 Feb 2008 08:50:18 -0800
From: Arjan van de Ven <arjan@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: Frans Pop <elendil@planet.nl>, linux-kernel@vger.kernel.org,
       Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: Unable to continue testing of 2.6.25
Message-ID: <20080218085018.05f3190a@laptopd505.fenrus.org>
In-Reply-To: <p73mypyxx6z.fsf@bingen.suse.de>
References: <200802171025.30590.elendil@planet.nl>
	<20080217124650.576990ce@laptopd505.fenrus.org>
	<p73mypyxx6z.fsf@bingen.suse.de>
Organization: Intel
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On Mon, 18 Feb 2008 13:31:48 +0100
Andi Kleen <andi@firstfloor.org> wrote:

> Arjan van de Ven <arjan@infradead.org> writes:
> >
> > the initial plan was for a depreciation period. Sadly it was
> > untenable since the API was changing entirely to fix bugs and add a
> > really important feature (the ability to clflush the exact range
> > rather than wbinvd'ing the caches of all cpus in the system), 
> 
> Just for the record: I posted full patches to implement clflush
> support some time ago without changing any exported API. So your
> claims that changing the API was needed to implement CLFLUSH are not
> correct.

yeah of course it is possible to make things "smart" by having hidden state.
doesn't make it right.

> 
> Also I believe some assumptions behind the new API are faulty (in
> particular that the caller doesn't fully own the to be changed pages)
> and make it actually impossible to implement the cache attribute PTE
> changing operation fully correct according to the Intel x86 manual
> (which requires temporary unmap)

the Intel x86 manual explicitly only has a temporary unmap when going from a 
cached state to a write-combining state. Any other transition does not require
an unmap. Which makes this not impossible, all a cached->WC transition needs
to do is go via an intermediate UC state and the really expensive process from
the manual is not needed.


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