Date: Mon, 24 Mar 2008 23:19:13 +0000 (GMT)
From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Glauber Costa <gcosta@redhat.com>
cc: linux-kernel@vger.kernel.org, akpm@linux-foundation.org,
       tglx@linutronix.de, mingo@elte.hu, ak@suse.de
Subject: Re: [PATCH 45/79] [PATCH] fix apic acking of irqs
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On Mon, 24 Mar 2008, Glauber Costa wrote:

> I see bit 7 - Illegal Register Address being set.

 Hmm, it looks like the only one to be reasonably set under these 
conditions, but I have never seen it reported for a read cycle to the EOI 
register anyway, so I suppose it has to be a relatively recent addition.

> I believe the reason we never saw it, is that the ESR register is not checked
> that often when interrupts are enabled. In the new bootup state machine, that

 Well, as I wrote, the error interrupt handler is always enabled, 
reporting the state recorded in the ESR register as soon as an error 
condition triggers and if an RMW cycle was a problem before, we would have 
seen a flood of reports from people -- like we indeed have many times for 
inter-APIC bus data corruption that triggers the same event (using bits 
3:0 in the ESR as relevant).

> is inherited from x86_64, we call do_boot_cpu with irqs clearly enabled, and
> check esr in the process.

 Please note that ESR may hold some leftover state from whatever happened 
before Linux has taken control, so it is reasonable and I think actually 
recommended by Intel (FWIW) to clear the register before enabling the 
error interrupt.  For how to clear the ESR properly, please see 
setup_local_APIC() -- subtle differences and errata in various APIC 
implementations have made it more complicated than necessary, sigh...

> But I can understand from the spec you posted that this is clearly an error.
> So I'd have better come up with a new solution from this

 Well, with CONFIG_X86_GOOD_APIC set there is no RMW access to the ESR as 
apic_write_around() expands to apic_write().  And the option is meant to 
be clear only for the original integrated APIC as included in the Pentium 
processor ("Pentium-Classic" in the Kconfig nomenclature).  I have no 
means to test such a system, but I still have a working dual-Pentium-MMX 
machine, which features local APICs that should be the same modulo errata.  
I may check and see whether a RMW cycle to the ESR triggers any problems 
with this computer, but the box is currently at the other end of the 
continent, so it will take a while.

 I have asked this question already: what kind of CPU are you running on?  
Do you really need to have CONFIG_X86_GOOD_APIC clear with it?

  Maciej
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