Message-ID: <47E90149.5040506@redhat.com>
Date: Tue, 25 Mar 2008 10:42:33 -0300
From: Glauber Costa <gcosta@redhat.com>
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To: "Maciej W. Rozycki" <macro@linux-mips.org>
CC: linux-kernel@vger.kernel.org, akpm@linux-foundation.org,
       tglx@linutronix.de, mingo@elte.hu, ak@suse.de
Subject: Re: [PATCH 45/79] [PATCH] fix apic acking of irqs
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Maciej W. Rozycki wrote:
>> is inherited from x86_64, we call do_boot_cpu with irqs clearly enabled, and
>> check esr in the process.
> 
>  Please note that ESR may hold some leftover state from whatever happened 
> before Linux has taken control, so it is reasonable and I think actually 
> recommended by Intel (FWIW) to clear the register before enabling the 
> error interrupt.  For how to clear the ESR properly, please see 
> setup_local_APIC() -- subtle differences and errata in various APIC 
> implementations have made it more complicated than necessary, sigh...
which excerpt specifically are you talking about ?
the only ESR mention I see in setup_local_APIC() is this:

          /* Pound the ESR really hard over the head with a big hammer - 
mbligh */
         if (esr_disable) {
                 apic_write(APIC_ESR, 0);
                 apic_write(APIC_ESR, 0);
                 apic_write(APIC_ESR, 0);
                 apic_write(APIC_ESR, 0);
         }
which seems more like a disablement.

the bootup code does clean it, tough, by writing and reading the ESR.

>> But I can understand from the spec you posted that this is clearly an error.
>> So I'd have better come up with a new solution from this
> 
>  Well, with CONFIG_X86_GOOD_APIC set there is no RMW access to the ESR as 
> apic_write_around() expands to apic_write().  And the option is meant to 
> be clear only for the original integrated APIC as included in the Pentium 
> processor ("Pentium-Classic" in the Kconfig nomenclature).  I have no 
> means to test such a system, but I still have a working dual-Pentium-MMX 
> machine, which features local APICs that should be the same modulo errata.  
> I may check and see whether a RMW cycle to the ESR triggers any problems 
> with this computer, but the box is currently at the other end of the 
> continent, so it will take a while.
> 
>  I have asked this question already: what kind of CPU are you running on?  
> Do you really need to have CONFIG_X86_GOOD_APIC clear with it?
> 
My testings that triggered that were with qemu, with randconfigs. 
Probably it has a good apic, but it is good that it triggered anyway. 
Otherwise I'd never see it.

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