Message-ID: <47EABBA5.8040508@s5r6.in-berlin.de>
Date: Wed, 26 Mar 2008 22:09:57 +0100
From: Stefan Richter <stefanr@s5r6.in-berlin.de>
User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.8.1.12) Gecko/20080219 SeaMonkey/1.1.8
MIME-Version: 1.0
To: linux-kernel@vger.kernel.org
Subject: memory-barriers.txt: cache coherency vs mmio
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Content-Length: 859
Lines: 26

The subject section in memory-barriers.txt says:

"[...] MMIO accesses may, in effect, overtake accesses to cached memory 
that were emitted earlier. A memory barrier isn't sufficient in such a 
case, but rather the cache must be flushed between the cached memory 
write and the MMIO access if the two are in any way dependent."

And the lowly driver programmer immediately asks:
How do I flush the cache?

In particular, do I have to do anyhing between

	coherent_dma_buffer->datum = something;

	writel(YOU_CAN_START_DMA_NOW, register);

Thanks,
-- 
Stefan Richter
-=====-==--- --== ==-=-
http://arcgraph.de/sr/
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/